12.1. The Diamond 545CK DSP Core’s Instruction Format
The Diamond 545CK DSP has several ISA extensions to the base Xtensa architecture that enhance DSP performance. These additions include a 16-entry, 160-bit vector register file, a vector DSP ALU with 20-bit precision per vector, eight 18×18-bit multiplier/accumulator (MAC) units, special-purpose function units for bit packing and unpacking and Viterbi decoding, a second load/store unit required for XY memory operations, and 32-bit input- and output-queue interfaces for high-speed I/O. These extensions were developed in conjunction with Berkeley Design Technology, Inc (BDTI), a firm that specializes in analyzing and benchmarking DSPs. The extensions improve the performance of a wide range of DSP tasks as reflected in the BDTImark2000 benchmark functions, listed in Table 12.1.
| Function | Description | Example application |
|---|---|---|
| Real Block FIR | Finite impulse response filter that operates on a block of real (not complex) data | Speech processing, for example, G.728 speech compression |
| Single-Sample FIR | FIR filter that operates on a single sample of real data | Speech processing, general filtering |
| Complex Block FIR | FIR filter that operates on a block of complex data | Modem channel equalization |
| LMS Adaptive FIR | Least-mean-square adaptive filter; operates on a single sample of real data | Channel equalization, servo control, linear predictive coding |
| Two-Biquad IIR | Infinite impulse response filter that operates on a single sample of real data | Audio processing, general filtering |
| Vector Dot Product | Sum of the point-wise multiplication of two vectors | Convolution, correlation, matrix multiplication, multi-dimensional signal processing |
| Vector Add | Point-wise addition of two vectors, producing a third vector | Graphics, combining audio signals or images, vector search |
| Vector Maximum | Find the value and location of the maximum value in a vector | Error control coding, algorithms using block-floating point |
| Viterbi Decoder | Decodes a convolutionally encoded bit stream | Wired and wireless communications, for example, cellular phones |
| Control | A contrived series of control (test, branch, push, pop) and bit manipulation instructions | Virtually all signal processing applications include some “control” code |
| 256-Point FFT | The Fast Fourier Transform converts a normal time-domain signal into the frequency domain | Radar, sonar, MPEG audio compression, spectral analysis |
| Bit Unpack | Unpacks words of varying length from a continuous bit stream | Audio and speech decompression |
Complex instructions can be built from the Diamond 545CK DSP’s operation primitives by bundling three operations into a wide instruction word, as shown in Figure 12.1. The Diamond 545CK DSP core’s 64-bit instruction format bundles two independent operations. The XCC (the Xtensa C/C++) compiler paired with the Diamond 545CK DSP core automatically performs the needed instruction bundling to use the core’s three-operation instruction word. XCC also automatically vectorizes code to take advantage of the processor’s 8-way MAC unit.
Figure 12.1. The Diamond 545CK DSP core is a static superscalar design that adds a third instruction format to the existing 16- and 24-bit Xtensa ISA instruction formats. The processor’s third instruction format is 64 bits wide, and this wide format bundles three independent operations.
All three instruction formats can be freely intermixed and tightly packed in memory. The Xtensa architecture’s inherent ability to handle differently sized instructions was a key enabler in the development of the Diamond 545CK DSP core’s design.