3.5. Memory Address Space

Data-space requirements for SOCs seem to grow without limit, especially for media-oriented chips. Consequently, the Xtensa ISA provides full, unrestricted 32-bit data-space addressing for its load and store instructions. The Xtensa ISA employs a Harvard architecture that physically separates instruction and data spaces, although they share the same 4-Gbyte address space. An Xtensa processor’s local memories are divided into instruction and data memories and the processor employs separate instruction and data caches.

The existence of local memories and caches, the address spaces allocated to the local memories, and the width of the bus interfaces to these local memories are all configuration options for Xtensa processors. Load, store, and fetch operations to addresses that are not allocated to local memories (as defined in the processor’s configuration) are directed to the Xtensa processor’s main bus interface, called the PIF (processor interface). The existence and width of a processor’s PIF bus is another Xtensa configuration option. (Note: All of these configuration options are preconfigured for Diamond Standard processor cores.)