5.7. Ports and Queue Interfaces

One of the most innovative I/O features of Xtensa and Diamond Standard Series microprocessor cores is the availability of TIE-defined ports and queue interfaces that connect the processors’ execution units directly to external devices using point-to-point (non-bused) connections. Ports are wires that either make specific internal processor state visible to external logic blocks (and other processors) or bring external signals directly into the processor where it becomes readable processor state. Xtensa processor cores have configurable ports and some pre-configured Diamond Standard Series cores have pre-configured input and output ports.

Similarly, Xtensa and Diamond queue interfaces are designed to connect directly to FIFO memories. Output queue interfaces connect to a FIFO’s inputs and drive data into the attached FIFO. Input queue interfaces connect to a FIFO’s outputs and accept data from the attached FIFO.

TIE queues allow Xtensa LX processors to directly interface to external queues that have standard push- and pop-type interfaces with full-and-empty hardware flow control. Xtensa port and queue interfaces can be configured to be from 1 to 1024 bits wide and an Xtensa processor can have as many as 1024 ports. Each queue interface actually consumes three TIE ports, so Xtensa processors are “limited” to “only” 340 or so queue interfaces, each up to 1024 bits wide.

Pre-configured Diamond cores have a predetermined number of ports and queues that varies with each core. The raw amount of I/O bandwidth represented by these ports and queue interfaces is unprecedented in microprocessor-based design.

TIE-defined instructions read data from input ports, write data to output ports, push data from the processor onto external queues, and pop data from external queues into processor state registers or register files. Suitably configured Xtensa processors can use the information from input queues directly in computations, bypassing an explicit “load from queue” instruction. Similarly, suitably configured Xtensa processors can store the information from a computation directly to an output queue as part of the computation, bypassing an explicit “store to queue” instruction. Some Xtensa and Diamond cores can perform simultaneous input and output operations over ports and queue interfaces.

An input queue interface connects to a FIFO output and brings data directly into the processor. Single-cycle instructions drive the ports and the queue interfaces, so port and queue transactions are much faster than PIF transactions. In addition, making connections to ports and queue interfaces requires less circuitry than attaching devices using a bus because no address decoding is needed for unshared, point-to-point connections. Addressing is implicit in point-to-point connections.