14.1. A Viable Alternative to Manual RTL Design and Verification
Configurable processors like Tensilica’s Xtensa cores can be used as alternatives to manually-coded RTL blocks. Application-tailored Xtensa cores use the same data-path structures as traditional RTL blocks: deep pipelines, parallel execution units, task-specific state registers, and wide data buses to local and global memories. Tailored, task-specific processors can sustain the same high-computation throughput and support the same data interfaces as RTL hardware designs.
Migrating an SOC design team’s design style from heavy use of RTL data paths and finite state machines (FSMs) to application-tailored processors with firmware control has many important implications:
Flexibility: changing the firmware is all that’s needed to change a block’s function.
Software-based development: Fast and low-cost software tools can be used to implement or modify most chip features.
Faster, more complete system modeling: For a 10-megagate design, even the fastest RTL logic simulator may not exceed a few simulation cycles per second. By contrast, firmware simulations for extended processors will run on instruction-set simulators at hundreds of thousands or millions of cycles per second.
Unification of control and data: No SOC consists solely of hardwired logic. There’s always at least one processor on the chip running software. Moving more RTL-based functions into processors removes artificial partitioning between control and data-processing functions.
Time-to-market: Using configurable processors simplifies SOC design, accelerates system modeling, and speeds hardware finalization. State machines implemented with firmware on an application-tailored processor can easily accommodate changes to standards or to the SOC’s functional definition.
Designer productivity: The engineering manpower needed to manually develop and verify hardware RTL is greatly reduced. A processor-centric SOC design approach permits graceful recovery when (not if) a bug is discovered through firmware changes instead of chip respins.
The benefits of being able to make changes in firmware rather than hardware with a processor-centric design approach cannot be understated. Application-tailored processor cores reduce the risks associated with state-machine design by replacing hard-to-design, hard-to-verify, hardware FSMs with pre-designed, pre-verified processor cores running FSM code.