3.2. Xtensa Registers

The Xtensa processor’s base ISA incorporates the following register files and registers:

• A 32-bit, general-purpose register file that employs register windows

• A 32-bit program counter

• Various special registers.

The Xtensa processor’s general-purpose 32-bit register file is shown in Figure 3.1. This file, called the AR register file, has either 32 or 64 entries (a configurable attribute). Xtensa instructions access this physical register file through a sliding 16-register window. Register windowing allows the Xtensa processor to have a relatively large number of physical registers while restricting the number of bits needed to encode a source or destination operand address to four bits each. Thus the 3-operand Xtensa processor instructions need only 12 bits to specify the registers holding the instruction’s three operands.