15.1. Grand Challenges and Disaster Scenarios

SOC designers have become increasingly unable to fully exploit all of the transistors available to them starting with the 90-nm process node in 2003–2004, as shown in Figure 15.1. The figure incorporates data presented by Gary Smith of Gartner Dataquest at DAC 2003 that is based on ITRS survey data and shows that silicon-manufacturing capacity and SOC-design capacity have tracked well since the widespread adoption of hardware-description languages (HDLs) in the early 1990s during the 1-micron era. HDLs first appeared years before, in the early 1980s, but did not become popular until gate- and transistor-level schematic drafting—the well-established IC-design method of the day—could no longer handle chip complexities of several hundred thousand gates. As Figure 15.1 shows, IC gate counts reached this level in the early 1990s.

Figure 15.1. Per-chip silicon capacity and the SOC-design team’s ability to exploit that capacity tracked well, until the 90 nm node.

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As IC gate counts grew, thanks to continuous improvements and revolutionary developments in IC manufacturing, IC-design teams got bigger to keep pace with the rising design load. However, Figure 15.1 shows that the current HDL-based design style seems to be reaching a plateau at around 50 million gates, just as the schematic-drafting design style reached its descriptive limits at a few hundred thousand gates. The HDL-based design style alone apparently cannot efficiently manage the complexity of larger chips. Figure 15.1 clearly shows that the gap between what can be designed and what can be manufactured is now increasing at a rapid rate.

The ITRS:2005 report minces no words about the state of SOC design:

Today, many design technology gaps are crises.

The ITRS:2005 report identifies five “grand challenges” related to SOC design:

Failure to adequately address all of these challenges would be disastrous for the electronics industry because it would curtail the rapid advancements that the commercial, consumer, and financial markets have come to expect from semiconductor advances and semiconductor vendors. Thus it’s possible to interpret failure to address the five grand challenges as five disaster scenarios for the electronics industry.