15.2.2. Avoiding Disaster Scenario 2: Excessive System Power Dissipation

A processor-centric SOC-design style directly addresses issues related to system power dissipation. Current ad hoc system-design styles waste power in many ways. Design efforts directed at saving transistors through processor multitasking and similar schemes drive on-chip clock rates ever higher, which drastically increases power dissipation. This design style, which evolved when transistors were expensive and chip power levels were low, is no longer valid in the era of nanometer ICs. The use of one or two multitasked, high-speed processors in an SOC also emphasizes the use of large, highly capacitive, global buses which also dissipate excessive power.

The processor-centric design style advocated in this book emphasizes the extensive exploitation of a task’s inherent parallelism and concurrency both inside of each processor—to keep processor clock rates low—and through the use of multiple processor cores—to reduce or eliminate multitasking, which drives processor clock rates up.

However, simply running each on-chip processor at the lowest possible clock rate doesn’t define the full extent of the processor-centric design style’s ability to reduce system power. Properly designed processor cores use extensive, fine-grained clock gating to minimize operating power on a cycle-by-cycle basis. Extensive clock gating is made possible by the processor’s fundamental operation. Processors execute instructions. Each instruction can be modeled and its functional needs mapped for each stage in the processor’s pipeline. The result is detailed knowledge of clocking requirements throughout the processor for every possible machine state.

Such knowledge is very difficult or impossible to obtain for manually coded RTL hardware and many design teams do not bother. Automated tools to insert clock gating into manually coded RTL hardware depend on exhaustive test benches to exercise the hardware in every conceivable situation. Creating such test benches is manually intensive work. Again, many design teams do not bother to perform this manual work because the schedule will not permit it.

In addition, it is easy to put a properly designed processor into a low-power sleep state and it’s similarly easy to awaken the processor when needed. This feature is especially handy when algorithms need to run intermittently. When the algorithm needs to run, the processor is brought out of the sleep state to run it. When the task is complete, the processor can go back to sleep.

Use of many processors to implement on-chip tasks also reduces the need for large, global buses because on-chip communications can more closely follow the actual communications needs of the collected on-chip tasks. Reducing the size and number of large, global buses also reduces SOC power dissipation.