8.4. The Diamond 212GP Processor Memory Map
Table 8.1 lists the address spaces assigned to the Diamond 212GP processor core’s two local memory interfaces and the XLMI port. Note that the instruction RAM and data RAM memory spaces are adjacent so they form one contiguous 256-Kbyte memory block from 0x3FFE0000 to 0x4001FFFF. The address space for the Diamond 212GP’s XLMI port is mapped to the same memory space as the Diamond 108Mini core’s second data memory, just below and contiguous with the address space for the data-memory block. All of the Diamond 212GP controller core’s three local memory spaces thus form one contiguous 384-Kbyte address space from 0x3FFC0000 to 0x4001FFFF.
| Local memory | Start address | End address |
|---|---|---|
| Local instruction RAM | 0x40000000 | 0x4001FFFF |
| Local data RAM #1 | 0x3FFE0000 | 0x3FFFFFFF |
| XLMI port | 0x3FFC0000 | 0x3FFDFFFF |
The Diamond 212GP controller core has a 32-bit, 4-Gbyte address space, so additional memory can be attached to its PIF bus if needed. However, the address spaces dedicated to local memory are hardwired to the appropriate local-memory and XLMI ports and memory transactions to those address spaces will not appear on the PIF bus. All Diamond processor cores including the Diamond 212GP automatically send memory accesses to non-local address locations out over the PIF bus.
Table 8.2 lists the Diamond 212GP controller core’s assigned reset, non-maskable interrupt (NMI), and other interrupt vectors. Note that the exception vectors for the Diamond 212GP controller core are assigned to locations located in non-local memory space, so at least some memory located at addresses 0x50000000 and 0x60000000 must be attached to the Diamond 212GP controller’s PIF bus to hold its reset and exception vectors. The processor’s timer interrupts and external interrupt pins are pre-assigned to various high-level interrupt vectors.
| Vector | Address |
|---|---|
| Reset | 0x50000000 |
| Base address for register window underflow/overflow exception vectors | 0x60000000 |
| Level 2 high-priority interrupt | 0x60000180 |
| Level 3 high-priority interrupt | 0x600001C0 |
| Level 4 high-priority interrupt | 0x60000200 |
| Level 5 high-priority interrupt | 0x60000240 |
| Debug exception | 0x60000280 |
| NMI | 0x600002C0 |
| Level 1 interrupt (Kernel mode) | 0x60000300 |
| Level 1 interrupt (User mode) | 0x60000340 |
| Double exception | 0x600003C0 |
Figure 8.3 shows the various important addresses mapped into the Diamond 212GP controller’s address space.
Figure 8.3. The Diamond 212GP controller core’s pre-configured address space maps the local instruction and data memories and the XLMI port into adjacent blocks in the address space.
The PIF implementation on the Diamond 212GP controller core is 32 bits wide. The PIF bus uses a split-transaction protocol and the Diamond 212GP controller core has an 8-entry write buffer to accommodate as many as eight simultaneous outstanding write transactions. The PIF also supports inbound-PIF operations, which means that external devices connected to the Diamond 212GP controller’s PIF bus can access the processor’s local memories through the processor’s PIF interface. This feature allows “glueless MP” systems to be built from multiple Xtensa and Diamond processor cores. The inbound-PIF portion of the Diamond 212GP controller core’s PIF implementation has an 8-entry request buffer.
The Diamond 212GP controller core has three internal 32-bit timers in that can be used to generate interrupts at regular intervals. The processor also has nine external, level-triggered interrupt input pins and one edge-triggered NMI pin.