5.9. Shared-Memory Topologies
A variety of system topologies employ shared memories to pass large amounts of data between processors in the system. With their many buses and memory interfaces, Xtensa and Diamond processors support a variety of such topologies. Figure 5.8 shows two processors sharing memory over a common multimaster bus. This is a simple and often-used architectural approach. Xtensa and Diamond processor cores can share memory in this manner over their main PIF buses because the PIF is designed to be a multimaster bus.
Sharing memory over a processors’ main buses is a simple inter-processor connection scheme but this approach can exhibit severe performance problems under high traffic loads because the single bus must handle all the traffic from both processors. In addition, the bus must also devote cycles to arbitrating access between the processors. In addition, each processor must, in turn, acquire control of the bus, access the memory, and then signal to the other processor that a memory transaction has been completed.
A method for sharing memory while lessening the bus overhead appears in Figure 5.9. Using this approach, each processor connects to the shared memory through a separate local bus and a hardware-memory arbiter controls access to the shared memory. The shared-memory arbiter can be a separate logic block, which then causes the shared-memory block to emulate a dual-ported memory, or the shared-memory block can be designed as a true dual-ported memory, in which case the memory incorporates the dual-port arbitration logic.
Because the local buses that connect the processors to the shared memory are not themselves shared resources in Figure 5.9, more bandwidth is available to the system and performance improves to the limit set by the shared memory’s bandwidth. Xtensa and Diamond processors can connect to shared, dual-ported memories over their XLMI and local RAM buses.
In addition, Xtensa and Diamond processor cores can directly access each other’s local memories over a common PIF bus using the processors’ inbound-PIF feature, as shown in Figure 5.10. The PIF supports reads and writes from external agents. Although this method for sharing memory is physically the same as the shared-memory scheme shown in Figure 5.8, it delivers better performance because only half of the shared-memory transactions are conducted over the PIF. The other half of the shared-memory transactions occur over the processors’ unshared local-memory buses, so PIF bandwidth requirements are reduced. Further, transactions can occur over each processor’s local memory bus simultaneously without creating a resource conflict. This additional concurrency further improves performance for systems that incorporate multiple processors.
Figure 5.10. Two Xtensa or Diamond processor cores can write to and read from each other’s local memory over a shared PIF bus using inbound-PIF operations.
