6.3. Diamond Standard Series Feature Summary

All Diamond Standard Series processor cores share a common base of 16- and 24-bit instructions. Some Diamond processor cores add 64-bit, VLIW-style instructions. Tensilica’s VLIW capability—called FLIX (flexible-length instruction extensions)—allows some of the Diamond Standard Series processor cores to issue and execute multiple independent operations per instruction. This feature significantly boosts application performance. Various key features of the Diamond Standard Series processor cores appear in Table 6.2.

Table 6.2. Significant Diamond Standard Series processor core features
Specialized functional units (not on every Diamond Standard Series processor core) Multipliers, 16-bit MAC, SIMD, VLIW
Memory management and memory protection
Region-based memory protection (108Mini, 212GP, 570T, 545CK, and 330HiFi) Full Linux MMU (232L)
Miscellaneous processor attributes
Little-endian byte ordering
5-stage pipeline
Exceptions: non-maskable interrupt (NMI), nine external interrupts, six interrupt priority levels, three 32-bit timer interrupts
32- or 64-entry windowed register file
Write buffer: 4/8/16 entries
Available interfaces
32-, 64-, or 128-bit PIF width to main system memory or to an on-chip system bus (Vera-based tool kit for PIF bridge implementation and verification)
Inbound-PIF requests allow external access to the processor’s local-memory buses
AMBA AHB-Lite interface available
Two 32-bit TIE ports for the 108Mini, 212GP, and 570T processor cores
Two 32-bit TIE queues for the 570T, 330HiFi, and 545CK processor cores
On-Chip memory architecture (depends on core)
2- or 4-way set-associative caches (all Diamond cores except 108Mini)
Write-through or write-back cache-write policy (all Diamond cores except 108Mini)
Line-based cache locking set-associative caches (all Diamond cores except 108Mini)
8- or 16-Kbyte instruction cache, 32- or 64-byte cache line (all Diamond cores except 108Mini)
8- or 16-Kbyte data cache, 32- or 64-byte cache line (all Diamond cores except 108Mini)
Designer-selectable number of data RAMs and instruction RAMs
Size of data RAM: 0/0.5/1/2/4/8/16/32/64/128 Kbytes
Size of instruction RAM: 0/0.5/1/2/4/8/16/32/64/128 Kbytes
Processor development and debug capabilities
C/C++ callable ISS
On-chip debug (OCD) capability: Trace and instruction/data breakpoint support (two hardware-assisted instruction breakpoints and two hardware-assisted data breakpoints)
GDB debugger support
ISS and Co-Simulation Model (CSM) support for Mentor Graphics’ Seamless CVE (Co-verification environment)
Software-development tools
High-performance Xtensa C/C++ compiler (XCC) and companion GNU tool chain
Eclipse-based Xtensa Xplorer Diamond Edition integrated development environment with graphical visualization capabilities
EDA environment support
Physical synthesis design flow for major EDA supplier tool sets (Cadence, Magma, Mentor Graphics)
Verification support
Comprehensive diagnostics for the core
Clock-cycle-accurate, pipeline-modeled ISS
OSKit overlay for supported real-time operating system
Nucleus from Accelerated Technology, Embedded Systems Division, Mentor Graphics
Linux from MontaVista Software
Bus designer’s toolkit (PIF kit) for bus-bridge design help

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