6.4. Diamond Standard Series Processor Core Hardware Overview and Comparison
This section highlights the major hardware blocks comprising the Diamond processor cores including the core register file and execution units, load/store units, issue width, external interfaces, and on-chip trace and debug units. Table 6.3 compares the major hardware features included in each Diamond core. Table 6.4 compares several key physical attributes of the six Diamond processor cores.
| Hardware features | 108Mini | 212GP | 232L | 570T | 330HiFi | 545CK |
|---|---|---|---|---|---|---|
| Instruction width (bits) | 16/24 | 16/24 | 16/24 | 16/24/64 | 16/24/64 | 16/24/64 |
| Multiple instruction issue (static superscalar) | No | No | No | 3 or 2 issue | 2 issue | 3 issue |
| Local-memory bus width (bits) | 32 | 32 | 32 | 64 | 64 | 128 |
| General-purpose registers | 32 | 32 | 32 | 32 | 32 | 64 |
| DSP vector registers | 8 × 48-bit and 4 × 56-bit | 16 × 160-bit | ||||
| Instruction-cache size (Kbytes) | N/A | 8 | 16 | 16 | 8 | NA |
| Instruction-cache associativity | N/A | 2-way | 4-way | 2-way | 2-way | N/A |
| Data-cache size (Kbytes) | N/A | 8 | 16 | 16 | 8 | N/A |
| Data-cache associativity | N/A | 2-way | 4-way | 2-way | 2-way | N/A |
| Load/store units | 1 | 1 | 1 | 1 | 1 | 2 |
| Local instruction RAM, selectable size, max size (Kbytes) | 128 | 128 | N/A | 128 | 128 | 128 |
| Local data RAM, selectable size, max size (Kbytes) | 128 (dual) | 128 | N/A | 128 | 128 (dual) | 128 (dual) |
| Local XLMI interface | No | Yes | No | Yes | No | No |
| 32-bit I/O ports | Yes | Yes | No | Yes | No | No |
| 32-bit I/O queue interfaces | No | No | No | Yes | Yes | Yes |
| Main bus interface (PIF) width | 32 | 32 | 32 | 64 | 64 | 128 |
| Zero-overhead looping | No | Yes | Yes | Yes | Yes | Yes |
| Sign-extend, NSA, MIN/MAX, CLAMPS instructions | Yes | Yes | Yes | Yes | Yes | Yes |
| Synchronization instructions | Yes | Yes | No | Yes | Yes | Yes |
| MUL16 instructions | No | Yes | Yes | Yes | No | Yes |
| 16/32-bit MAC16 instructions | No | Yes | Yes | Yes | No | No |
| MUL32 Instructions | No | No | No | Yes | No | No |
| Audio instructions | No | No | No | No | Yes | No |
| Specialized DSP instructions | No | No | No | No | No | Yes |
| External interrupts | 9 | 9 | 9 | 9 | 9 | 9 |
| Timer interrupts | 3 | 3 | 3 | 3 | 3 | 3 |
| Non-maskable interrupt | 1 | 1 | 1 | 1 | 1 | 1 |
| On-chip debug (OCD) | Yes | Yes | Yes | Yes | Yes | Yes |
| Diamond core | Maximum frequency (MHz) (0.13G WC) | Dhrys. 2.1 MIPS/MHz | Die area[*] (mm2) (0.13G) | Gate count | Instruction width | mW/MHz (0.13G) |
|---|---|---|---|---|---|---|
| 108Mini | 250 | 1.2 | 0.41 | 47K | 16/24 bits | 0.09 |
| 212GP | 266 | 1.3 | 0.68 | 73K | 16/24 bits | 0.135 |
| 232L | 233 | 1.3 | 0.84 | 84K | 16/24 bits | 0.145 |
| 570T | 250 | 1.52 | 1.13 | 114K | 16/24/64 bits | 0.20 |
| 330HiFi | 220 | 1.3 | 1.33 | 142K | 16/24/64 bits | 0.18 |
| 545CK | 230 | 1.3 | 2.93 | 310K | 16/24/64 bits | 0.196 |
| Note: All area, power, and frequency are representative only, and subject to variation based on the process technology, cell library, and design tools used. | ||||||
[*] Area is post synthesis, post layout, assuming 85% routing efficiency.
The feature sets of each pre-configured Diamond core were set so that these six ISA-compatible processor cores provide the SOC designer with a wide range of core size and performance, and a broad selection of features. The cores’ physical attributes range widely, tracking the wide range in capabilities among the cores.