8.8. System Design with the Diamond 212GP Processor Core
Figure 8.6 shows a system built with one Diamond 212GP controller core and three Diamond 108Mini processor cores. The 4-processor cores can communicate with each other and with global memory over the shared 32-bit PIF bus. A bus arbiter controls access to the PIF bus. This system closely resembles the system shown previously in Figure 7.5 but the Diamond 108Mini master processor in that system has been replaced by a Diamond 212GP processor in the system shown in Figure 8.6. The Diamond 212GP processor on the left of the figure is configured as the system master and the three Diamond 108Mini processor cores are slaves.
Figure 8.6. This multi-processor system design allows the master Diamond 212GP processor (shown on the left) to control the operation of the three Diamond 108Mini slave processors through their Reset, Run/Stall, and NMI inputs.
As with the system shown in Figure 7.5, the four processor cores shown in Figure 8.6 can communicate with global memory over the shared 32-bit PIF bus and with each other’s local memories using the Diamond processor cores’ inbound-PIF feature. A bus arbiter controls access to the PIF bus. Local/Global address-translation blocks attached to each processor’s PIF bus perform the critical function of mapping the attached processor’s local address space into one unified global address map.
Three wires from the master processor’s direct output port are connected to the Reset inputs of the three Diamond 108Mini slave processors; three more output-port wires are connected to the slave processors’ Run/Stall inputs; and yet another three output-port wires are connected to the slave processors’ NMI inputs. The Diamond 212GP controller core is equipped with the same 32-bit output port as the Diamond 108Mini processor core so the master/slave connections of this system are unchanged from the system discussed in the previous chapter.
This system configuration allows the master processor to independently reset and halt all three slaves. The three slave processors are automatically reset when the master processor is reset because the reset-initialized state of all port pins on the master processor’s 32-bit output port is zero. Inverters attached to the master processor’s output-port wires that are used for resetting the slave processors will therefore assert the slave processors’ Reset inputs when the master processor is reset.
After initializing itself, the Diamond 212GP master processor can assert the Run/Stall input to each slave processor and then remove the reset signal to each Diamond 108Mini slave processor. While each slave processor is stalled, the master processor can transfer program code from the large global memory (or from its own local memory) to each slave processor’s local instruction memory using inbound-PIF write operations—which can occur even while the slave processors are stalled. One advantage this system has over the 4-processor system discussed in the previous chapter is that the Diamond 212GP master processor has a cache, which gives it better performance when executing code directly from PIF-attached global memory.
When the master processor releases a slave processor’s Run/Stall input, the slave processor will commence program execution starting at its reset-vector address. Because the Diamond 108Mini processor’s reset vector is set to 0x50000000, each slave processor’s first instruction fetch will be directed to the PIF-connected global memory. That first instruction however can set up a jump to a location in the slave processor’s local instruction memory, which will then isolate the slave’s operations from the PIF bus.
This scheme allows two of the Diamond 108Mini slave processors to independently execute code from their local memories concurrently while the Diamond 212GP master processor is programming or reprogramming the third slave processor’s instruction memory. Together, these four processors consume approximately 2 mm2 on the SOC die and the resulting multiprocessor system will exhibit even better processing performance than the system shown in the previous chapter because the master processor in this system has instruction and data caches.
The three Diamond 108Mini slave processor cores shown in Figure 8.6 still should not execute code directly out of the global memory attached to the PIF bus because they have no instruction or data caches and memory transactions on local-memory buses are about five times faster than the same transactions conducted over the PIF bus. However, the Diamond 212GP master processor does have instruction and data caches so its performance will be good even when executing code from PIF-connected global memory.
Although all four processors still must share the PIF bus, this system design would devote most of the PIF bandwidth to the master processor and the slave processors would use the PIF sparingly. The addition of caches to the master processor in this 4-processor system changes the use dynamics for the shared-bus architecture and allows the system to get much better performance when compared to the system consisting of four cacheless processors, at the expense of additional silicon for the slightly larger Diamond 212GP controller core plus the RAM arrays for its caches.
Similar to the discussion of the Diamond 108Mini-based, 4-processor system in Chapter 7, when a Diamond 108Mini slave processor in the system shown in Figure 8.6 enters the WAITI mode, it asserts its PWaitMode status output. The Diamond 108Mini slave processors’ PWaitMode outputs are connected to the Diamond 212GP master processor’s input port so that the master processor can evaluate the running status of the slave processors. Due to the Diamond 212GP controller core’s 32-bit input port, this is a glueless connection, which means that the Diamond 212GP master processor need not consume bus bandwidth to poll the status of the other processors in the system. Bus bandwidth can be reserved for moving instructions and data around the system.