9.3. The Diamond 232L CPU Memory Map
The Diamond 232L CPU core’s entire address space is mapped to the PIF bus. The processor directs all instruction fetches, loads, stores, and cache spills and fills through the PIF. Table 9.1 lists the Diamond 232L CPU core’s assigned reset, non-maskable interrupt (NMI), and other interrupt vectors. The Diamond 232L’s reset and exception vectors are assigned to locations located in high memory, so some memory must be located at addresses 0xD0000000 to 0xD00003FF and 0xFE000000. In reality, the Diamond 232L CPU will be used for running large operating systems, so a large part of this upper address space will be populated with PIF-attached RAM.
Figure 9.3 shows the various important addresses mapped into the high memory addresses of the Diamond 232L CPU’s uniform address space.
Figure 9.3. The Diamond 232L CPU core’s pre-configured address space maps the reset and interrupt vectors to the high addresses in the processor’s memory map.
The PIF implementation on the Diamond 232L CPU core is 32 bits wide. The PIF bus uses a split-transaction protocol and the Diamond 232L processor core has an 8-entry write buffer to accommodate as many as eight simultaneous outstanding write transactions.
The 212GP processor core has three internal 32-bit timers in that can be used to generate interrupts at regular intervals. The processor also has nine external, level-triggered interrupt input pins and one edge-triggered, NMI pin.