13.6. GALS On-Chip Networks

GALS (globally asynchronous, locally synchronous) NoCs address another growing problem in SOC design—one noted by the ITRS. There’s no escaping the conclusion laid down by the ITRS:

. . . as it becomes impossible to move signals across a large die within one clock cycle or in a power-effective manner, or to run control and dataflow processes at the same rate [best effort versus guaranteed service], the likely result is a shift to [an] asynchronous (or, globally asynchronous and locally synchronous (GALS)) design style.

This statement melds two SOC design problems: maintaining a constant clock skew across a large chip and efficiently conveying best-effort and guaranteed-service traffic among many blocks in a complex SOC.

The GALS approach to NoC design represents one way to attack these two problems. It recognizes the difficulty of maintaining near-constant clock skews across a complex SOC by discarding the effort entirely. Complex SOCs are already partitioned into many self-contained blocks (as demonstrated in the many SOC block diagrams shown in this chapter) and the GALS approach allows each of those blocks to be internally synchronous—they can even run at different clock rates—but inter-block communications is asynchronous, which eliminates the need for a global, low-skew reference clock. Commercial GALS design tools, such as the CHAINworks tool suite offered by Silistix, are just starting to appear on the market.