5.5. Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF

Xtensa and some Diamond Standard Series microprocessor cores have dedicated RAM and ROM ports for local instruction and data memories. In addition, the Xtensa ISA includes an optional, configurable XLMI data port for high-speed connection to local memories and other device types. Local memories do not incur the same silicon overhead as a memory-cache way, because simple local memories (as opposed to caches) do not have tag arrays.

Each memory interface and the XLMI port have a busy signal that can be used to indicate that the associated memory is being used by some logic external to the processor (or that the memory is otherwise unavailable) and that the processor cannot immediately execute a fetch, load, or store transaction with the selected memory. The memory-busy signals can be used to, among other things, share a memory between multiple processors, or to allow external logic to load the local memory. Note: ROM ports do not permit write operations; RAM and XLMI ports do.

The Xtensa and Diamond Standard Series microprocessor cores have a main-bus interface called the PIF (processor interface) that supports load, store, and instruction-fetch transactions initiated by the processor as well as inbound transactions initiated by a device external to the processor (including other processors). Inbound-PIF read and write operations can be directed at a processor’s local memories so that the data stored in those memories can be read or modified by external devices.