- Copyright
- In Praise of Designing SOCs with Configured Cores...
- About the Author
- The Morgan Kaufmann Series in Systems on Silicon
- Foreword
- Preface
- Acknowledgements
- Introduction to 21st-Century SOC Design
- The Start of Something Big
- Few Pins = Massive Multiplexing
- Third Time’s a Charm
- The Microprocessor: A Universal System Building Block
- The Consequences of Performance—in the Macro World
- Increasing Processor Performance in the Micro World
- I/O Bandwidth and Processor Core Clock Rate
- Multitasking and Processor Core Clock Rate
- System-Design Evolution
- Heterogeneous- and Homogeneous-Processor System-Design Approaches
- The Rise of MPSOC Design
- Veering Away from Processor Multitasking in SOC Design
- Processors: The Original, Reusable Design Block
- A Closer Look at 21st-Century Processor Cores for SOC Design
- Bibliography
- The SOC Design Flow
- Xtensa Architectural Basics
- Basic Processor Configurability
- Processor Generation
- Xtensa Processor Block Diagram
- Pre-Configured Processor Cores
- Basics of TIE
- TIE Instructions
- Improving Application Performance Using TIE
- TIE Registers and Register Files
- TIE Ports
- TIE Queue Interfaces
- Combining Instruction Extensions with Queues
- Diamond Standard Series Processor Cores—Dealing with Complexity
- Bibliography
- MPSOC System Architectures and Design Tools
- SOC Architectural Evolution
- The Consequences of Architectural Evolution
- Memory Interfaces
- Memory Caches
- Local ROM and Local RAM Interfaces, the XLMI Port, and the PIF
- The PIF
- Ports and Queue Interfaces
- SOC Connection Topologies
- Shared-Memory Topologies
- Direct Port-Connected Topologies
- Queue-Based System Topologies
- Existing Design Tools for Complex SOC Designs
- MPSOC Architectural-Design Tools
- Platform Design
- An MPSOC-Design Tool
- MPSOC System-Level Simulation Example
- SOC Design in the 21st Century
- Bibliography
- Introduction to Diamond Standard Series Processor Cores
- The Diamond Standard Series of 32-bit Processor Cores
- Diamond Standard Series Software-Development Tools
- Diamond Standard Series Feature Summary
- Diamond Standard Series Processor Core Hardware Overview and Comparison
- Diamond-Core Local-Memory Interfaces
- The PIF Main Bus
- Diamond-Core Ports and Queues
- Diamond Standard Series Core Instructions
- Zero-Overhead Loop Instructions
- Miscellaneous Instructions
- Synchronization Instructions
- 16-bit Multiply and Multiply/Accumulate Instructions
- 32-bit Multiply Instructions
- Diamond-Development Tools
- Other Specialized Diamond Standard Series Processor Instructions
- Choosing a Diamond
- Bibliography
- The Diamond Standard Series 108Mini Processor Core
- The Diamond 212GP Controller Core
- The Diamond 232L CPU Core
- The Diamond 570T Superscalar CPU Core
- The Diamond 330HiFi audio DSP Core
- 300 Instructions Boost Audio Performance
- The Diamond 330HiFi: A High-Performance audio DSP Core
- Diamond 330HiFi audio DSP Core Interfaces
- The Diamond 330HiFi audio DSP Core’s Memory Map
- The Diamond 330HiFi audio DSP Core’s Cache Interfaces
- The Diamond 330HiFi audio DSP Core’s (Region-Protection Unit)
- Input- and Output-Queue Interfaces
- System Design with the Diamond 330HiFi audio DSP Core
- Bibliography
- The Diamond 545CK DSP Core
- Using Fixed Processor Cores in SOC Designs
- Beyond Fixed Cores
- A Viable Alternative to Manual RTL Design and Verification
- The Conventional, Embedded Software-Development Flow
- Fit the Processor to the Algorithm
- Accelerating the Fast Fourier Transform
- Accelerating an MPEG-4 Decoder
- Boost Throughput with Multiple Operations per Cycle
- High-Speed I/O for Processor-Based Function Blocks
- The Single-Bus Bottleneck
- Alone, Faster is Not Necessarily Better
- Bibliography
- The Future of SOC Design
5.8. SOC Connection Topologies
The large number and variety of interfaces on Xtensa and Diamond Standard Series processor cores creates a very wide architectural-design space. The PIF, local memory, and XLMI buses support all of the system topologies shown in Figures 5.1–5.5. In addition, the large number of buses, ports, and queues available on Xtensa and Diamond processor cores allows these processors to be employed in many novel system architectures that provide much higher I/O bandwidth than was previously possible with conventional microprocessor-based designs.
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