2.6. Communication Alternatives
As discussed earlier, the classic method used to interconnect SOC blocks is to use one or more microprocessor-style buses. This design style is a holdover from decades of microprocessor-based system-design experience. Buses are still useful for conveying inter-block traffic, but they are by no means the SOC designer’s only alternative. A partial list of alternative interconnection schemes includes:
Buses
Shared memories
FIFO queues
Simple wires (point-to-point connections)
On-chip networks
Buses and bus hierarchies are familiar to all system designers. Figure 2.11 shows a system that uses a bus hierarchy to move data around a system that contains two processors and a hardware accelerator block.
Shared or dual-port memories are common in systems that transfer large blocks of data between successive computational elements. The shared memory can hold data blocks such as network packets or video frames. Figure 2.12 shows a shared-memory system. Shared-memory subsystems are good for implementing systems where multiple computational blocks need random access to data within the data block.
Figure 2.13 illustrates a system that employs FIFO memories for inter-processor communications. Unlike shared memories, FIFOs are unidirectional, so the system needs two FIFOs if large amounts of data must be passed back and forth between the computational elements. If the amount of data to be transferred is not equal in both directions, the two FIFOs need not even be the same size. However, FIFOs are fast because there’s no contention for the port to shared-memory. One computational element controls the FIFO’s head and the other controls its tail. The FIFO’s head and tail are separate resources.
If the amount of information to be transferred between computational blocks is small, FIFOs and shared memories may be too complex. Simple wires may suffice. Often, these wires originate from a writeable register attached to one computational element and terminate in a readable register attached to the other computational element. Figure 2.14 illustrates such a system. When data-transfer requirements are relatively simple, wires represent a low-cost way of connecting computational elements.
Finally, considerable research is currently going into developing on-chip networks. Although this work is largely beyond this book’s scope, you’ll find some on-chip networking concepts discussed in the final chapter.
One of the advantages of the MPSOC design style advocated in this book is that the methodology allows the SOC design team to experiment with the various interconnection schemes listed above and to measure, through simulations of the incrementally refined system model, how the system architecture responds to the use of the different interconnection methods. In general, the design team should be looking for the lowest-cost interconnection method that meets system-performance goals. However, it’s always a good idea to provide a healthy amount of design margin for the unanticipated specification changes or next-generation goals that appear unexpectedly, and often in the middle of the project cycle—often at the least convenient moment.