9.7. System Design with the Diamond 232L CPU Core

Figure 9.9 shows a software-coherent, symmetric-multiprocessing (SMP) system built with four Diamond 232L CPU cores (each with their own local memory) and a large global memory. The four processor cores communicate with each other through the global memory over the shared 32-bit PIF bus. A bus arbiter and locking device control access to the PIF bus. This hardware design can be used to implement either a message-passing or shared-memory SMP system.

Figure 9.9. This multi-processor system design allows four Diamond 232L CPU cores to form an SMP system.

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This system allows a group of cooperating Diamond 232L CPU cores to execute multiple independent tasks under the control of an SMP operating system. Access to shared global memory must be performed under some sort of mutual exclusion (mutex) mechanism. Figure 9.9 shows a combination hardware bus arbiter and locking device that provides mutex-governed access to global memory.

Many SMP systems are designed with hardware cache coherency. In such systems, each processor snoops the transactions occurring on the main bus and tracks the memory traffic of the other processors, invalidating its own cache when needed. Hardware cache coherency requires substantial extra silicon to implement the cache-snooping logic for each processor. It is possible to realize most of the benefits of hardware-cache-coherent systems without implementing the cache-snooping hardware by using software cache coherency. Software-cache-coherent systems require that the processors in the system have explicit control of their caches, which the Diamond 232L core does.

Together, the four Diamond 232L processor cores in this system require only 3.2 mm² on the SOC, implemented in a 130 nm, G-type process technology. The various cache, local, and global memory arrays naturally consume additional silicon depending on size.

The hardware system shown in Figure 9.9 can easily be scaled using a step-and-repeat design process. For example, Figure 9.10 shows an 8-processor version of the same system. All of the same SMP code and mutex mechanisms developed for the 4-processor system can be adapted to the 8-processor system so the operating-system code should need only minimal changes to accommodate the four extra CPUs. The eight Diamond 232L processor cores shown in this system require only 6.4 mm² on the SOC (when implemented in a 130 nm, G-type process technology), so this 8-processor system is still rather small.