5.6. The PIF

The configurable PIF is the main-bus interface for Xtensa and Diamond Standard Series microprocessor cores. Xtensa PIFs can be configured to be 32, 64, or 128 bits wide. Pre-configured Diamond Standard Series processor cores have pre-configured PIF widths and the width depends on the Diamond core selected—higher performance Diamond cores have wider PIFs.

All Xtensa and Diamond core PIFs support single-data transactions (transactions that are less than or equal to the size of the data buses) as well as block transactions where several data-bus widths of data are input or output using multiple PIF-transaction cycles. The PIF employs a split-transaction protocol that accommodates multiple outstanding transaction requests. The PIF-transaction protocol is easily adaptable to a variety of on-chip inter-processor communication schemes.

Like transactions on all microprocessor main buses, PIF transactions occur over several clock cycles. Such is the nature of buses that support ready/busy handshaking, split transactions, and multiple bus masters. Xtensa and Diamond processor cores have faster buses, the XLMI port and the local-memory interfaces, which do not support split transactions or multiple masters, but even these buses require multiple clock cycles to effect a transaction.

Because buses are shared resources, bus protocols must give target slave devices sufficient time to decode the target address presented on the bus at the beginning of the transaction cycle. Consequently, bus transactions are not the fastest possible I/O transaction protocols because bus-transaction speeds do not approach the data rates of direct connections that are one of the hallmarks of RTL hardware design. For applications that require even more I/O bandwidth, Xtensa and Diamond processor cores offer direct ports and queue interfaces.