10.1. The Diamond 570T: A High-Performance CPU Core

The Diamond 570T CPU architecture contains all of the basic elements of the Xtensa ISA. It has a 32-entry general-purpose register file, a 5-stage execution pipeline and 32-bit addressing. It has two additional execution pipelines giving the processor core the ability to execute three independent instructions per clock. The Diamond 570T CPU’s three execution pipelines are not symmetric, as shown in Figure 10.2. The first execution pipeline, associated with operation slot 0, contains the base Xtensa ALU, a 32-bit multiplier, a branch unit, and the processor’s load/store unit.

Figure 10.2. The Diamond 570T processor core implements a high-performance, 3-way superscalar, 32-bit RISC CPU while consuming only 1.46 mm² of silicon and approximately 275μ W/MHz when implemented in a 130 nm, G-type process technology. In a 130 nm LV process technology, the Diamond 570T CPU can run at 233 MHz and consumes less than 1 mm² of silicon.

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The Diamond 570T’s second execution pipeline contains a second base Xtensa ALU, a second multiplier, and a second branch unit. Thus both of the first two Diamond 570T execution pipelines can execute the full Xtensa arithmetic and logical instruction set including branches and can also perform 32-bit multiplication. The first execution pipeline alone is responsible for executing load and store instructions. The Diamond 570T’s third execution pipeline contains a third Xtensa ALU and can execute the full Xtensa arithmetic and logical instruction set. The XCC compiler for the Diamond 570T CPU core understands the unique nature of each of the three Diamond 570T execution pipelines and automatically bundles instructions accordingly.

The Diamond 570T CPU core also incorporates the Diamond Series processor core software-debug stack, as shown on the left of Figure 10.2. This debug stack provides external access to the processor’s internal, software-visible state through a 5-pin IEEE 1149.1 JTAG TAP (test access port) interface and through a trace port that provides additional program-trace data.