7.3. The Diamond RPU
Early microprocessors of the 1970s had one unified memory space. As microprocessor usage became more sophisticated, microprocessors started to run multiple tasks and single, unified memory spaces became cumbersome because the unified memory space allowed independent tasks to easily access to memory regions assigned to other tasks. This lack of inter-task memory barriers resulted in spectacular system crashes, which gave rise to the use of the RTOSs to manage the multiple tasks. All of the Diamond Standard Series processor cores except for the 232L core provide hardware support for memory protection through an RPU.
Note: The 232L CPU core incorporates a memory-management unit (MMU) that supports more complex operating systems such as Linux. The access modes used in the TLB contained in the 232L’s MMU are similar to those implemented in the TLBs contained in the RPUs of the other Diamond cores.
As Figure 7.4 illustrates, the Diamond RPU divides the processor’s 4-Gbyte memory space into eight equally sized, 512-Mbyte regions. The Diamond 108Mini processor core’s two local data-memory address spaces fall into memory-protection region 1 and its local instruction-memory address space falls into memory-protection region 2. Thus the RPU can prevent accidental writes to instruction memory through the proper use of its protection mechanisms. The Diamond 108Mini core’s non-local address space (assigned to the PIF) falls into all eight memory-protection regions, so the 108Mini controller core’s RPU is also useful for managing access to PIF-attached memory and devices.
Figure 7.4. The Diamond cores’ RPU divides the processors’ memory space into eight protected regions and the Diamond 108Mini core’s local data and instruction memories map into memory-protection regions 1 and 2, respectively so the RPU can prevent accidental writes to instruction memory through the proper use of its protection mechanisms.
The Diamond processor sets the memory-protection attributes for each region independently by setting 4-bit access-mode values in separate, 8-entry, instruction and data TLBs. Each TLB has an entry for each of the eight memory-protection regions.
The TLB access modes control both the protection level and the cache behavior for each of the eight memory-protection regions. The access modes appear in Table 7.3 and descriptions of the modes appear in Table 7.4.
| Access-mode value | Access-mode name | Instruction-fetch behavior | Load behavior | Store behavior |
|---|---|---|---|---|
| 0000 | No allocate | Instruction-fetch exception | No allocate | Write-through/No allocate |
| 0001 | Write-through/No write allocate | Allocate | Allocate | Write-through/No write allocate |
| 0010 | Bypass | Bypass | Bypass | Bypass |
| 0011 | Not supported | Undefined | Load exception | Store exception |
| 0100 | Write-back mapped region with write-back cache option | Allocate | Allocate | Write-back/Write allocate |
| Write-back mapped region allocate without write-back cache option | Allocate | Allocate | Write-through/No write | |
| 0101–1101 | Reserved | Instruction-fetch exception | Load exception | Store exception |
| 1110 | Isolate | Instruction-fetch exception | Direct processor access to memory cache | Direct processor access to memory cache |
| 1111 | Illegal | Instruction-fetch exception | Load exception | Store exception |
Note: Because the Diamond 108Mini processor core has no instruction or data caches, it ignores all of the TLB’s cache-related attributes and always acts as though cache-bypass mode is set. For completeness, Tables 7.3 and 7.4 list all of the Diamond RPU TLB’s access-mode behaviors for all Diamond cores including the cache-access controls not supported (or needed) by the Diamond 108Mini processor core.