14.7. High-Speed I/O for Processor-Based Function Blocks

The two bottlenecks in high-speed SOC block design are I/O performance and computational performance. The previous sections in this chapter have discussed improvements in a processor’s computational performance through TIE-based extensions. This section and following sections discuss the ways that TIE can be used to improve a processor’s I/O performance.

Every microprocessor core’s main bus represents a major I/O bottleneck. All data into and out of the processor must pass over this main bus. Consequently, two factors constrain I/O traffic in and out of the processor. First, a bus can only perform one transfer at a time so other pending transfers must wait for the current transfer to clear. Second, because processor main buses are designed to accommodate many system configurations, they tend to require multiple cycles to effect bus transactions. As a result of these limitations, processor cores have lacked the I/O bandwidth required by many tasks performed in SOCs.

Tensilica’s Xtensa LX processor incorporates several features that allow an SOC design team to improves its I/O bandwidth through application-specific tailoring. In fact, these features allow the Xtensa LX processor to deliver I/O transfer rates that can match those achieved by manually designed hardware RTL blocks. However, the Xtensa LX processor achieves high I/O data rates with automatically generated, pre-verified hardware that greatly reduces the time required to design and verify the SOC. In addition, the resulting function block is firmware-programmable, which means that it can be changed at a later date to accommodate a new or revised industry standard, to add a feature, or to fix a bug in the system design without changing the silicon.

The key features that allow the Xtensa LX processor to achieve these high data-transfer rates are TIE ports and queue interfaces, which allow designers to add many new input and output ports that lead directly into and out of the processor’s execution unit. Most of the Diamond Standard series processor cores have ports or queue interfaces, which have been discussed in previous chapters. Each Diamond core (except for the Diamond 232L CPU core) has a pair of 32-bit ports, a pair of 32-bit queue interfaces, or both. The Xtensa LX processor can have as many as 1024 ports and each port can be as wide as 1024 bits. Consequently, it’s possible to add as many as one million I/O pins to an Xtensa LX processor.

The Xtensa LX ports and queues can be directly invoked by instruction extensions written in TIE, so that input and output operations become implicit in the execution of a computation. This approach maximizes I/O bandwidth in a manner quite similar to the high I/O bandwidth achieved by manually designing function blocks using RTL. However, the processor-based approach requires much less effort from the SOC development team to design and verify the hardware because the Xtensa LX processor is generated automatically by Tensilica’s Xtensa Processor Generator.