9.4. The Diamond 232L Cache Interfaces
Processor cache memories use fast, small RAM arrays to buffer the processor from the slower and larger memories generally located external to the processor core or the SOC. The Diamond 232L CPU core’s data and instruction caches store data and instructions that a program is immediately using, while the rest of the data and program reside in slower main memory—RAM, or ROM. In general, the Diamond 232L CPU core can access instruction and data caches simultaneously, which maximizes processor bandwidth and efficiency.
The Diamond 232L processor incorporates a pre-configured version of the Xtensa cache controller that operates separate, 16-Kbyte, 4-way, set-associative, instruction and data caches. The data cache employs a write-back (as opposed to write-through) write policy. The Diamond 232L processor’s cache memories accelerate any program the processor executes by storing copies of executed code sequences and data in fast cache memory. The caches provide faster access to instructions and data than can memories attached to the processor’s PIF.
The cache controller is woven (integrated) into the Diamond 232L processor core so the processor has direct interface ports to the sixteen RAM arrays used for storing cached data and cache tags. Each cache way requires separate RAM arrays for cache data and cache tags so sixteen RAM arrays are needed to complete the Diamond 232L CPU core’s cache memory. These RAM arrays are external to the processor’s core. Figure 9.4 shows how the eight RAM arrays attach to the processor core’s cache interface ports. In all respects except for the number of ways, the Diamond 232L CPU’s caches work identically to those of the 212GP controller core, as discussed in Chapter 8.
Figure 9.4. The 232L processor core incorporates a cache controller that runs separate, 4-way set-associative, 16-Kbyte instruction and data caches. The processor has direct interfaces for the sixteen RAM arrays—used for storing cached data and cache tags.
