1.6. Increasing Processor Performance in the Micro World
Lacking the access to the high clock rates previously available to PC processor designers, processor core designers must turn to alternative performance-enhancing strategies. Use of additional buses and wider buses are both good performance-enhancing strategies for SOC-centric processor design. In the macro world of packaged microprocessors, additional processor pins incur a real cost. Packages with higher pin counts are more expensive, they’re harder to test, and they require more costly sockets. However, in the micro world of SOC design, additional pins for wider buses essentially cost nothing. They do incur some additional routing complexity, which may or may not increase design difficulty. However, once routed, additional pins on a microprocessor core do not add much to the cost of chip manufacture, except for a fractionally larger silicon footprint.
In much the same way, additional microprocessor buses also incur very little cost penalty but provide a significant performance benefit. Processor cores for SOCs often have many more buses than their packaged counterparts, as shown in Figure 1.9.
Figure 1.9. SOC processor cores can incorporate several buses to increase performance without incurring the pin limitations and costs of packaged processors.
Figure 1.9 shows a hypothetical processor core with eight buses. One of those buses, the main one, is the traditional multimaster bus that all microprocessors have had since 1971. Four of the buses communicate directly with local data and instruction memories. Two more buses communicate with instruction and data caches, respectively. The remaining bus is a fast local bus used for high-speed communications with closely coupled devices such as FIFOs and high-bandwidth peripherals.
The processor shown in Figure 1.9 has two load/store units plus an instruction-fetch unit, which can operate three of the processor’s buses simultaneously. In addition, the processor’s cache-control unit can independently use the cache buses and the memory buses. As a consequence, several of the buses on the processor shown in Figure 1.9 can be operating simultaneously. This sort of I/O concurrency is precisely what’s needed to keep the processor core’s operating frequency low, and thus keep operating power low as well. The number of pins required to implement eight buses is cost-prohibitive for a packaged processor IC, but is not at all costly for a processor core.