Chapter 8. The Diamond 212GP Controller Core
The name Jeep came from the abbreviation used by the army for “General Purpose” vehicle, G.P.
The Diamond 212GP controller core is a general-purpose, 32-bit RISC processor core. Like the Diamond 108Mini core, the Diamond 212GP controller has interfaces for local instruction and data memories but it also includes a cache controller that operates 8-Kbyte, 2-way set-associative instruction and data caches for efficient execution of large programs. Even with the addition of a cache controller, the processor consumes 0.7 mm2 of silicon and 195 W/MHz when implemented with a 130 nm, G-type (general-purpose) process technology. The Diamond 212GP controller core brings many performance benefits of a 32-bit RISC processor to bear on the designated tasks:
Large 4-Gbyte address space
32-bit computations
Large 32-entry register file
Separate 8-Kbyte, 2-way, set-associative instruction and data caches
5-stage pipelined operation resulting in a 250-MHz maximum clock rate in 130 nm technology.
The Diamond 212GP controller core has a 32-bit version of the general-purpose processor interface (PIF) bus for global SOC communications. An optional AMBA bus bridge supplied with the 232L processor core adapts the PIF to peripheral devices designed for the AMBA AHB-Lite bus. Like the Diamond 108Mini processor core, the Diamond 212GP core has interfaces for local instruction and data RAMs. However, instead of two data-RAM interfaces like the Diamond 108Mini core, the Diamond 212GP controller core has one data-RAM interface and an XLMI interface port. The XLMI port can be used as a data-RAM interface but it includes signals that permit devices with read side effects to deal with speculative read transactions. The Diamond 212GP core also incorporates direct input and output ports that can accelerate I/O.