8.5. The 212GP RPU
The Diamond 212GP controller core uses the same RPU discussed in the previous chapter. However, the Diamond RPU’s cache-access modes are operational in the Diamond 212GP processor because it has instruction and data caches.
Figure 8.4 shows how the Diamond RPU divides the Diamond 212GP processor’s 4-Gbyte memory space into eight equally sized, 512-Mbyte regions. The Diamond 212GP controller core’s local data-memory address space and the address space assigned to the XLMI port fall into memory-protection region 1. Its local instruction-memory address space falls into memory-protection region 2. Thus the RPU can prevent accidental writes to instruction memory through the proper use of its protection mechanisms. The Diamond 212GP core’s non-local address space (assigned to the PIF) falls into all eight memory-protection regions, so the Diamond 212GP controller core’s RPU is also useful for protecting PIF-attached memory and devices.
Figure 8.4. The Diamond 212GP core’s RPU divides the processor’s memory space into eight protected regions. The processor’s local data memory address space and XLMI port map into memory-protection region 1 and its local instruction-memory address space maps into memory-protection region 2 so the RPU can prevent accidental writes to instruction memory through the proper use of its protection mechanisms.
The Diamond 212GP controller sets the memory-protection attributes for each region independently by setting 4-bit access-mode values in separate, 8-entry instruction and data TLBs. (Note: the three-letter abbreviation TLB stands for translation lookaside buffer but, for Diamond processor core RPUs, its definition is widened to mean “translation hardware.”) Each TLB has an entry for each of the eight memory-protection regions.
The access modes control both the protection level and the cache behavior for each of the eight memory-protection regions. The access modes appear in Table 8.3 and descriptions of the modes appear in Table 8.4.
| Access-mode value | Access-mode name | Instruction-fetch behavior | Load behavior | Store behavior |
|---|---|---|---|---|
| 0000 | No Allocate | Instruction-fetch exception | No allocate | Write-through/No allocate |
| 0001 (see Note) | Write-through/No write allocate | Allocate | Allocate | Write-through/No write allocate |
| 0010 | Bypass | Bypass | Bypass | Bypass |
| 0011 | Not supported | Undefined | Load exception | Store exception |
| 0100 | Write-back | Allocate | Allocate | Write-back/Write allocate |
| 0101–1101 | Reserved | Instruction-fetch exception | Load exception | Store exception |
| 1110 | Isolate | Instruction-fetch exception | Direct processor access to memory cache | Direct processor access to memory cache |
| 1111 | Illegal | Instruction-fetch exception | Load exception | Store exception |
| Note: RPU access-mode 1 forces Diamond core data caches to operate in write-through mode even though all Diamond processor core data caches are pre-configured as write-back caches. | ||||
| RPU access mode | Access-mode description |
|---|---|
| No allocate | Do not allocate a cache line for this address. If the address is already cached, fetch or load the cached value. If the address has an allocated cache line but the cache line is not already in the cache, fetch or load the value from main memory and place the value in the cache. |
| Bypass | Do not use the cache. |
| Write-back | Write the value to the cache and then update main memory when the cache line is evicted or when the processor forces the cache line to be written to main memory. |
| Isolate | Permits direct read/write access to the cache’s data and tag RAM arrays. |
| Illegal | Any access causes an exception. |
Note: Tables 7.3 and 7.4 from the previous chapter are repeated in this chapter as Tables 8.3 and 8.4 because the RPUs for the Diamond 212GP and Diamond 108Mini controller cores use the same access-mode definitions but act differently due to the absence of caches in the Diamond 108Mini core.