3.8   HISTORICAL BACKGROUND

3.8.1   Early Work

The origins of much of today's FPGA research are in work in the late 1960s and early 1970s on cellular arrays. This work was mainly concerned with improving the fault tolerance of logic structures, thus allowing larger silicon areas or whole wafers to be used to implement logic. The method proposed was to cover the wafer with a regular array of restructurable cells capable of implementing general logic functions. Both fuse- and flip-flop-programmed structures were proposed and investigated. Important early work in this area was done by Manning [Mann77], Minnick [Minn64], Wahlstrom [Wahl67], and Shoup [Shoup70]. A good survey article of the early research appears in [Minn67].

3.8.2   PALs and Structured PALs

The first programmable two-level logic products were PROMs from Harris and Monolithic Memories. Monolithic Memories later introduced field-programmable logic-array (FPLA) devices based on bipolar fusible link technology, and later Birkner and Chua at Monolithic Memories invented the PAL architecture that was to dominate the marketplace, replacing TTL as the method of choice for implementing glue-logic functions.

The PAL concept was further improved with the introduction of GAL devices. These devices were erasable either electrically or by UV light and used low power CMOS rather than bipolar technology. The most popular of these devices, the 22V10 can emulate a wide variety of conventional PALs.

Structured PALs were introduced and popularized by Altera Corporation, which was founded in 1983 to provide a field-programmable alternative to mask-programmable gate arrays.

3.8.3   FPGAs

The Xilinx FPGA architecture was designed by Ross Freeman and introduced in a paper in the 1986 Custom Integrated Circuits Conference [Carter86].

The Actel FPGA architecture [Actel90] and antifuse technology was designed by a team led by Amr Mohsen and Abbas El Gamal, and was described in a series of papers early in 1988 [Mohsen88], [El-Ayat88].

3.8.4   Computational Arrays

The Algotronix CAL device [Algo91] was introduced in a paper presented at the Decennial Caltech Conference on VLSI in 1989 [Gray89], based on an architecture developed in 1985 as part of Tom Kean's Ph.D. research [Kean89]. Concurrent Logic [Conc91] introduced the CFA600 Series in 1991 as the result of long-term work on cellular arrays by its founder Fred Furtek. The Pilkington Microelectronics “sea of gates” architecture was designed by Kenneth Austin and licensed to GEC/Plessey as the electrically-reconfigurable architecture (ERA) [Pless91].

3.8.5   VLSI Primitives and Programming

A more detailed but less current treatment of the VLSI design issues of FPGA architectures is presented in [Kean89]. Textbooks on CMOS design are [Weste85] and [Glass85]. These books also provide good introductory treatments of RAM cell design. A useful survey article of nonvolatile MOS memory technology, including newer flash memory technology, appeared in [Pash89].

The PLICE antifuse technology is described in [Osann88]. An antifuse allowing metal-to-metal connections with much lower resistance than the PLICE technology is the basis of a more recent FPGA family [QL91].

Studies on soft error rates in Xilinx FPGAs are contained in [Xilinx92]. A description of an FPGA that continually checks its control store is in [Felton91].

3.8.6   Benchmarking

The first serious attempt to benchmark FPGA circuits against traditional gate arrays was done by Actel Corporation [Osann88]; [Wein91] gives a comparison of Xilinx and Actel devices over a set of benchmark circuits. Various academic groups have used benchmark circuits to evaluate commercial FPGAs and suggest architectural improvements [Rose92] or to support novel architectural ideas [Walkup92].

SUMMARY: HOW TO CHOOSE AN FPGA

Let's assume that you have to select an FPGA for a new project and have received literature from about 20 possible contenders. Where do you go from here?

Stage 1. Elimination Trials

In this stage you should eliminate any architectures that cannot meet the following criteria (at this point you should believe manufacturers' claims since the objective is to weed out “no-hopers” before doing more detailed analysis).

1. Does the part appear to be reasonably priced?
2. Does the part have reasonable density and performance (PREP numbers)?
3. Has the part been in production for more than a year? If it hasn't been, then you probably won't be able to get one, and if you do, it could have unforeseen glitches.
4. Can you see at least ten realistic designs done using this architecture either in the manufacturer's literature or published elsewhere? If the part fails this criterion, then you should ignore any benchmark claims and reject it. Note that this point refers to the architecture: a new part based on an established architecture is worth considering.
5. Do you think the manufacturer will still be making them next year? This point refers both to large corporations that may leave the FPGA business or completely change their architecture by licensing another product, as well as to small start-ups that might go bankrupt.

Under exceptional circumstances (e.g., if only one supplier can offer a required feature) an architecture which fails here may go forward into the next round.

Stage 2. Comparative Evaluation

At this stage you should be left with at most five strong contenders, all of which are probably capable of doing the job. You should evaluate them based on the following criteria:

1. Start-up Costs. There are time and money costs associated with introducing a new FPGA. CAD software in particular is expensive, complex, and requires time to learn. Programmers, in-circuit emulators, and other development hardware also cost money. If you or someone within your organization has used a particular device before, are happy with it, and have the support technology on hand, then you should probably go with it.
2. Generality. It is usually worth choosing an FPGA that is more general-purpose over a specialized one more suited to your application because the more general device could be used in other projects within your organization. This means you get more value for the time and money invested in getting started with the new device.
3. Speed and Density for Your Application. You should be able to estimate these elements using a pencil and paper. If you cannot do so, then this is a black mark against the architecture. Naturally, the technology must be able to meet your speed and density requirements. If your application cannot fit on a single chip, then you must evaluate how easy it is to split designs over multiple chips. If your design is relatively small, then you should evaluate the range of parts available to ensure that you can buy one that fits your application for a reasonable price (rather than just a large, high-priced part).
4. Can you see an example of the device being used successfully in a similar application to yours? If so, then this is a very good reason for going with the device.
5. Board Level Costs. You should evaluate the extra circuitry required at the board level (if any) to support the FPGA.
6. Heat and Power. With the exception of bipolar PAL devices, which can have extreme power requirements, heat and power requirements of programmable devices are moderate. However, a battery-based application might provide a strong reason for choosing one architecture over another.
7. Manufacturing Costs. You should evaluate any additional costs associated with manufacturing boards that use the FPGA (e.g., FPGA programming costs).
8. Reliability. You should ensure that the FPGA meets the reliability standards required by your application.
9. Technological Leadership. It is often worth choosing a device based solely on its technological leadership; this can translate to technological leadership for your product. Working with leading-edge technology is rewarding if you are prepared for and can afford the inevitable glitches.

PROBLEMS

These questions are intended to bring out real-world issues covered in the chapter. There are no right or wrong answers. The material in the body of the chapter should be helpful in tackling the questions, but your own background knowledge and experience is equally important. Some of the questions are included because the writer would like to know the answers!

1. Dynamic RAM technology offers considerable density improvements over the static RAM used in FPGAs. What are the main obstacles to its use in this application and how can they be overcome? (Hint: Consider the refresh cycle, a background in VLSI design may be helpful.)
2. How well-suited are the following classes of logic block for implementation in a structured PAL: 16-bit adder, multiplier, address decoder, DMA request/acknowledge, and control logic? Where appropriate suggest an alternative, more effective implementation.
3. The following benchmark has been proposed for a comparative evaluation of the density afforded by various FPGA devices:

   (a) Identify product die size and technology.

   (b) Identify the largest and smallest macro that will fit in a single logic cell. Size is measured using a table of equivalent gates required to implement the macro in a gate array technology (e.g., XOR scores 3,2-input AND scores 1). Average the result to yield the average gate count per logic cell.

   (c) Multiply the average gate count per cell by the number of cells per device.

   (d) Derate the result by a utilization factor based on the percentage of cells whose functions can be used after placement and routing of a set of benchmark circuits.

   Identify at least two critical failings of this methodology and comment on how it could be improved.

4. You have been approached by General Roman Pica, President of the island republic of Sans Serif (check a map of the Indian Ocean if you don't remember your geography), who has asked you to develop a spy satellite. You do not have access to ASIC technology, and because of functionality and board area requirements must use a commercial FPGA for critical circuits. You are likely to be assassinated if the system fails during its 10-year design lifespan. Which FPGA technology would you choose and why?
5. It has been suggested that a device consisting of a RISC microprocessor core surrounded by an FPGA would be very well-suited to embedded processor applications, such as laser printer controllers. The FPGA would provide a very flexible interface between the microprocessor and the print engine or other logic. Does this idea make sense? What should the interface be between the processor core and the FPGA? Are there any important disadvantages (device pin-out limitations?)
6. An obvious extension of FPGA architecture is to include analog functions within the pad ring to reduce chip count in mixed signal applications. Suggest suitable analog primitives for inclusion and outline methods of interfacing them to the digital core or the device. Is it possible to design such a device with a general enough analog section to be worth marketing?
7. Outline a procedure for determining the configuration of an EP1810 (or more recent structured PAL) with its security fuse blown. Assume you have access to a well-equipped laboratory and a large number of devices to test. Suitable approaches might include applying vectors to the device or trying to reconfigure parts of the configuration store to eliminate the inputs from some product terms while mapping the effects of others. Would some opaque paint, a microscope, a steady hand, and a UV lamp come in handy?
8. Antifuse technology offers an advantage over fuse-based technology in channeled gate array architectures because only those devices corresponding to wires required by the user's circuit need to be programmed. Do antifuses offer the same benefits in PAL-type devices? Suggest reasons why there are no commercial antifuse-based PALs.
9. The Actel ACT1 module has three 2:1 multiplexers and a 2-input OR gate, with a total of nine inputs and one output. There are 547 modules in the A1020A part, which has 69 user input/output pins. How many should there be if Rent's formula applies, assuming an exponent of 0.5?
10. How would you provide a synchronizer circuit for an asynchronous input to a Xilinx XC3000 design?
11. Even a synchronizer may fail from time to time, if an input signal changes during its set-up and hold “window.” Suggest a way of reducing the problem, even if it can't be totally eliminated.
12. Suggest three separate advantages of in-circuit reprogrammable FPGAs over fuse-programmable FPGAs.
13. Sketch the circuit for a 6-transistor static RAM cell. Assuming a minimum-size transistor has channel width and length of 2 micron and 1 micron, respectively, mark the width and length values for each transistor that is likely to give reliable operation.
14. The Actel ACT1 FPGA uses the circuit shown in Fig. 3–6. How would you implement the function Y = A + B + C?

BIBLIOGRAPHY

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