Abstract circuit, 13
Adder, 137–142, 144–147, 158, 179, 181
Algotronix CAL, 71–73, 96, 143, 147, 165–167, 184, 197–200, 202, 212, 216, 221–223, 229, 236
Altera:
American Micro Devices PAL, 66
Antifuse, 60, 63, 83–84, 88, 322
Application-specific integrated circuit, 2, 7, 9, 322
ASIC, see Application-specific integrated circuit
Atmel, 260. See also CLi6000
Bit stream downloading, 143, 307, 308
Boolean algebra, 28
Boolean function, 30
Boolean function unit, 55, 73–74
Boundedness, 37
CAL, see Algotronix CAL
Capital, 273
Cell-based integrated circuit, 7, 11, 322
Channel, 10
Channel architecture, 8
Channelless (sea-of-gates), 282
CHS2×4 custom computer, 184, 185–189, 210, 217
Clean-room technology, 269
Clocking, 24
Combinational circuits, 28–30, 137–143
Commodity components, 265
Computational logic array, 55, 70–71
Concurrent Logic, 96
Configurable hardware paradigm, 15–17
Configurable logic block, 57–60, 287
Control store, 2, 73, 81, 87, 89, 96
Data encryption (example), 190–205
Data Encryption Standard, 190
Decade counter, 143, 149–150, 152–155
behavioral, 20
hierarchical, 20
physical, 20
technology-independent, 21
temporal, 23
Design methodologies, 18
Design process flow:
application-specific integrated-circuit, 116–121
programmable logic device, 113–116
Design security, 3
Design tools, 104
Direct interconnect, 57
Dynamic programming algorithm, 215
Dynamic random-access memory, 2
Dynamic reconfiguration, 3, 88, 94, 264, 277, 286, 303, 319
Electrically-erasable programmable read-only memory, 82–83
Electrically-programmable read-only memory, 81–82, 87
Electron-beam inspection, 272
Electrostatic discharge, 47
Field-programmable circuit board, 295
Field-programmable gate array:
arrays of, 264
as memory, 287
channeled, 55
evolution, 2
market, 261
marketshare, 263
programming, 81
simulation, 110
Field-programmable interconnect:
architecture, 304
chip, 293
device, 308
general, 291
Fixed-function look-up table, 74
Flip-flop:
D-type, 31
event-triggered D-type, 207–209
toggle, 31
Fluid flow simulation, 225
Framestore controller, 170–179
Fuse, 83
Gajski-Kuhn diagram, 19, 116, 117
Gate array, 8
Genetic string comparison:
distance evaluation, 214, 218–225
dynamic programming algorithm, 25, 216
self-timed implementation, 218–225
Hardware description language, 104, 106, 108
Hardware paradigm, 15
Input/Output block, 289
Intellectual property, 268
JTAG (IEEE 1149.1), 290, 304, 306
Latch, 31
Library of Parameterized Modules, 319
Linear feedback shift register, 157
Liveness, 38
Mask-programmable gate arrays, 265–267
Mead-Conway style, 22
Mealy machine, 32
Muller C-element, 206–208, 211, 220
Multiplexer-based look-up tables, 73–74
Multiplier:
NeoCAD, 312
Noise margin, 45
Non-disclosure agreement, 270–272
Non-recurring engineering charges, 262, 266
PALASM2, 107
Paper trail, 269
Parameterized modules, 123
Patents, 268
Pipelining, 13, 25, 198, 219, 221–222, 237, 287
Place (Petri Net), 37
Place-and-route acceleration, 232–236
Placement-and-routing, 111, 129, 141, 177, 179, 287, 315, 318
Plessey, 282
PLICE antifuse, 84
Processor-memory-switch representation, 18
Programmable array logic, 54, 64, 95
Programmable Electronics Performance Corporation, 94
Programmable interconnect, 292
Programmable logic device, 11, 12
Programmable logic era, 11
Programmable logic market, 262
Programmable read-only memory, 54
Prototyping, 267
Pseudorandom number generation, 151
RAM look-up table, 73
Random testing, 151
ROM generator, 123, 125, 127–129
ROM synthesis, 116
Scalability, 56
Sea-of-Gates, 282
Security, 89
Self-timed environment prototype, 205, 206
Semiconductor Chip Protection Act, 268
Sequential circuit, 31
Seven-segment decoder, 104–107, 109, 110
Sipal propagation, 46
Signature analysis, 155, 159–160
Silicon compilation, 125
Simulated annealing, 141
Small Business Innovation Research, 274
Small Business Technology Transfer, 274
SPLASH, 184
State machine:
general, 32
Static random-access memory, 81–82, 86
Structured PAL, 55, 64–65, 67–69
Subtractor, bit-serial, 248
Switch matrix, 290
Synchronizer, 50
Technology mapping, 28
Token, 37
Toshiba, 282
Trade Secret, 269
Traffic light controller, 32, 33, 41
Transistor-transistor logic, 2, 6
Transition, 37
Von Neumann architecture, 13, 15, 16
Xilinx:
XC3000, 56–60, 76, 80, 137–138, 140–141, 154–156, 171, 173, 176–180, 184
18.119.126.80