6.2   ARCHITECTURE OF THE CHS2×4

The architecture of Algotronix’s configurable array logic (CAL) technology [Algo91] is particularly suited to the building of arrays of chips to form a single computing surface [Gray89]. The CHS2×4 and its associated software have been designed and built to explore this aspect of FPGA usage.

The CHS2×4 contains up to 9 CAL1024 chips and 2M bytes of static RAM. Two boards can be connected together to form a system with a 4 × 4 array of CAL chips for computation and up to 4M bytes of static RAM. The CHS2×4 board is supported by the configurable logic software (CLS) software suite, including a graphical editor and an on-line debugger, and a library of interface routines that can be called from the user’s C programs.

6.2.1   Hardware Architecture

Architecturally the CHS2×4 system consists of three hardware subsystems (see Figure 6–1). These are:

1. PC interface and control subsystem.
2. computation subsystem.
3. memory subsystem.

The bus architecture, Figure 6–2 allows the memory subsystem and CAL configuration memory of the computation subsystem to be read and written from the host processor. Configuration memory and the memory subsystem share an address space local to the board. In addition, the computation array may execute memory operations, using the counter as an address register, synchronized to the host clock.

Figure 6–1. CHS2×4 board. Figure courtesy of Xilinx, Inc. ©Xilinx, Inc. 1991. All rights reserved.

Figure 6–2. CHS2×4 block diagram. Figure courtesy of Xilinx, Inc. ©Xilinx, Inc. 1991. All rights reserved.

The four main busses on the CHS2×4 board interconnecting the major subsystems shown on these figures are:

1. Address Bus (A[0..21]). This bus is used to address the CAL control store, the static RAM data memory and the EPROM that contains the power-up configuration for the control CAL.
2. Low Data Bus (LD[0..7]). This is the main data bus on the board and connects the PC data bus, the CAL control store, the data memory, and the initial configuration EPROM.
3. High Data Bus (HD[0..7]). This bus is used in conjunction with LD[0..7] to allow 16-bit transfers between the PC, the data memory, and the computation array inputs and outputs. In addition, the computation array can simultaneously read 8 bits from the memory and write 8 bits to the memory using LD and HD together.
4. Control Bus (Mode[0..2]). The mode bits of the control bus determine the use to which the data busses will be put, as detailed in Table 6-1.

The PC interface-and-control subsystem has the task of handling communications with the host PC/AT and controlling transfers on the internal busses of the CHS2×4. For maximum flexibility this subsystem is based around a CAL1024 chip whose configuration is loaded from an EPROM when the PC/AT is reset or powered up.

TABLE 6-1. Bus Usage Modes

The CHS2×4 is accessed through 16 locations in the PC/AT’s input/output (I/O) space using a protocol implemented by the control CAL. The bottom four bits of the address bus during a board access are used to determine the operation to be performed, which is completed during the same I/O cycle. This technique is faster than using an I/O cycle to transfer an instruction to the board, followed by a second cycle to transfer the associated data.

The computation subsystem of the CHS2×4 board consists of a 2 × 4 array of CAL1024 chips and appropriate address decoding for their control store, which provides random access to cells within the array for defining logic circuits and sensing function unit outputs. Access to the periphery of the array is available via the system busses and a number of connectors. At the north boundary the four CALs are fully pinned out to a 128-way header connector. This connector may be used to connect to a neighboring CHS2×4 board, allowing a large system containing a 4 × 4 array of CAL chips to be built. The west boundary of CAL_0,1 is fully pinned to a 37-pin DIN connector, which appears on the back panel edge of the PC/AT board. This connector may be used to directly connect external devices to the board. This bus is also connected to the west boundary of the control CAL to provide communication between the computation array and the control subsystem—this could be used, for example, to indicate the termination of an algorithm running on the computation array. In addition, at the east boundary, the high data (HD) and low data (LD) busses connect to every fourth boundary cell. At the west boundary of CAL_0,0 both the HD and LD busses are connected to boundary cells. These connections support transfers to and from the on-board memory.

The memory subsystem provides the computation array with high bandwidth access to a large local data memory, thus supporting systolic and pipelined computations where data are streamed through the CAL array. It contains four 32-pin sockets for static RAMs and associated address decoding. These sockets can be filled with 128K × 8 SRAM chips, 128K × 8 SRAM hybrids or 512K × 8 SRAM hybrids. If all four sockets are filled with 512K hybrids, a 2M-byte memory is provided.

The software support for the CAL architecture and the CHS2×4 custom computer consists of a computer-aided engineering (CAE) environment and an applications environment. This is shown diagrammatically in Figure 6–3.

The CLS CAE environment contains components for both automated and manual CAL configuration. It consists of the following programs

• clare   The configurable logic array editor (clare) is a graphical tool for manipulating cellular designs. The user builds a design as a hierarchy of blocks, each of which may contain individual configurable cells and instances of other blocks. Point-to-point routing within blocks may be interactive or automatic via a maze router. The editor supports physical design, in a symbolic form, by allowing the user to allocate cells. At the same time, structural design is supported by allowing the user to display nets and manage interblock and intracell wiring. Designs are saved in a text file, the .cfg file, that is read by other programs to produce the bit patterns to personalize a CAL chip or CHS2×4 board.
• laura and libcal   laura is the equivalent of a block generator in ASIC chip design. The purpose of laura is to provide a programming interface that designers can use to produce and manipulate .cfg files. laura is intended to complement clare by facilitating parameterization of layouts. Basic library elements may be generated manually and then manipulated algorithmically. This is particularly useful in producing highly regular systolic designs. libcal provides routines for reading and writing the Algotronix data file formats and defines the main data structures used by Algotronix programs.
  

  

  Figure 6–3. Software architecture. Figure courtesy of Xilinx, Inc. ©Xilinx, Inc. 1991. All rights reserved.

• lisa   The lisa program generates CAL configuration .cfg files suitable for placement and routing with the clare graphical editor automatically from truth tables.
• edif2cfg   The edif2cfg program automatically generates CAL configuration .cfg files suitable for placement and routing with clare, automatically from Electronic Design Interchange Format (EDIF) netlists, which in turn can be created by the OrCAD or ViewLogic schematics packages.
• cfg2edif   The cfg2edif program extracts netlist and timing information from placed-and-routed CAL designs.
• cfg2cal   The cfg2cal program generates binary programming information for a given CAL board from a .cfg file, output by the clare graphics editor or another tool. cfg2cal can also generate hex files for use by EPROM programmers to allow CALs to be used in stand-alone applications.

The CAL architecture offers the designer unique facilities for monitoring and changing the internal state of an FPGA in real time. The debbie program provides an interactive debugging environment for users of the CHS2×4 board. debbie provides windows to monitor the state of internal cells on the CAL array and the values in the memory and counter register on the CHS2×4 board. The values produced by individual cells are displayed as either a red (for logic 1) or blue (for logic 0) band above the corresponding gate. Cell functions and routing are determined by decoding the array control gate. Cell output logic values are determined by reading back the cell output bit of the control store and not by simulation of the user’s design.

The CHS2×4 board is controlled via an applications program running on the PC/AT, which takes charge of disk access and displaying results as well as computations not suited for implementation on CALs. Thus, the support software for the CHS2×4 board takes the form of a library of C routines lib2×4, which can be called from an applications program written by the user.

As well as allowing access to the local memory for transfer of data and results, these routines provide for access to the CAL’s control store. This permits dynamic reconfiguration of individual resources, such as routing multiplexers and function units, as well as monitoring cell outputs. It is also possible to programmatically clear any latch in the circuit implemented on CALs. The software tracks the mapping of gate component names in the user’s schematic to cell coordinates, allowing reference to gates by name in the user’s control program. This feature means the user programs that access the CAL control store need not be changed when the design placement changes. It is also possible to reconfigure the control CAL using the C library to provide new ways of accessing the board within a given application.