While the concept of truly dynamic reconfiguration has been known for some time, there have so far been few applications that justify its complexities. Rapid reconfiguration increases the number of pins that must be totally dedicated to this purpose.
Several companies, including Atmel and PMeL, have announced their intention to exploit dynamic reconfiguration. For example, the Atmel Cache Logic* concept allows newly required functions to be loaded into an FPGA while inactive functions are kept in an adjacent memory.
Clearly, the gate count of FPGAs will continue to increase as finer detailed very-large-scale integration (VLSI) processes continue to develop. FPGAs have the same attraction as memory to fabricators, that is, they are highly regular and the end application is of little concern. But there are differences as well as similarities, and the provision of a routing network that is generous enough for all applications and yet fast is a particular challenge.
ALTERA CORPORATION
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San Jose, CA 95134
APTIX CORPORATION
225 Charcot Avenue
San Jose, CA 95131
I-CUBE, INC.
2328-C Walsh Avenue
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PILKINGTON MICROELECTRONICS LTD.
Sherwood House
Gadbrook Business Center
Rudheath, Northwich, Cheshire CW9 7TN, U.K.
XESS CORPORATION
2608 Sweetgum Drive
Apex, NC 27502
XILINX INC.
2100 Logic Drive
San Jose, CA 95124
Section 8.2.1 was contributed by Robert Hartman of Altera, Inc.
Section 8.2.2 was contributed by Gareth Jones of Pilkington Microelectronics Ltd.
Section 8.2.3 was contributed by Bradly Fawcett of Xilinx, Inc. Section courtesy of Xilinx, Inc. © Xilinx, Inc. (1994). All rights reserved.
Section 8.3.1 was contributed by Dr. Amr Mohsen of Aptix, Inc.
*FPIC is a trademark of Aptix Corporation.
† FPCB is a trademark of Aptix Corporation.
Section 8.3.2 was contributed by Shrikant Sathe of I-Cube. Inc.
Section 8.4.1 was contributed by Dr. David E. Van den Bout of XESS Corporation.
Section 8.5.1 was contributed by Carle Churgin of NeoCAD Inc.
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