6.1   THE STATE OF THE ART

As we saw in Chapter 3, the use of FPGA devices as computing structures is motivated by the perceived performance and price performance advantages of hardware customized for a particular application, over more general-purpose computing structures. In particular we can identify the following key advantages:

1. There is no overhead associated with fetching and decoding instructions.
2. Bus structures can be tailored to the operation: for example, an operation that had five input operands and one output could have five input buses and one output bus, allowing it to complete in a single cycle. On a conventional architecture, assuming all operands were in memory, at least six cycles of the shared data bus would be required.
3. Arithmetic units can be provided for nonstandard operations.
4. Operation units need be no longer than required. For example, if we are operating on 8-bit data, we would use an 8-bit adder; this adder could be four times smaller and faster than a 32-bit adder in a conventional machine.
5. Because tailored operation units are smaller we can have more of them, thus allowing a more parallel solution to increase performance.
6. When the computer is intended to process a stream of high bandwidth input data, the peripheral interface itself can be implemented on the programmable device. In these applications the speed at which the host can transfer data from the peripheral to the special-purpose computer through its bus would not be a bottleneck.

The main disadvantage of configurable hardware as a computing medium is the difficulty of hardware design compared to software design. Configurable computing structures are therefore, most suited to relatively simple operations that must be repeated many times, and are usually proposed as accelerators within conventional computers.

At the present time, there are several commercially available configurable hardware computers targeted at application-specific integrated-circuit (ASIC) emulation, for example [D’Amour89]. More general-purpose configurable hardware computers are becoming available. At the time of writing there are three fully developed systems:

1. The Paris Research Laboratory of Digital Equipment Corporation has developed supercomputer class configurable hardware add-on boxes for DEC workstations [Bertin89]. These systems can be configured with multiple boards each of which contains 25 Xilinx chips (XC3020’s or XC3090’s) and fast RAM memory. Benchmark results for this system configured to solve ten real-world applications are presented in [Bertin92].
2. SPLASH [Gokh91] is a two-board add-on to a SUN workstation containing 32 Xilinx 3090 programmable gate arrays and 32 memory chips closely associated with the Xilinx chips. The architecture is optimized for a particular problem—pattern matching DNA sequences—and in this application routinely achieves speed-ups of 10 to 1 over a single processor Cray 2.
3. The Algotronix CHS2×4 custom computer was developed as a demonstration system for the CAL1024 chip and is an add-on board for PC/AT class computers. It is a relatively low-cost system and is currently in use in more than 30 universities and research laboratories, mainly in Europe.

In this chapter we use the CHS2×4 as a concrete example of a configurable hardware computer and describe several applications for it that illustrate some typical techniques.