CONTENTS
TRADEMARKS AND PROPRIETARY NAMES
1. System Implementation Strategies
1.2 Design and Implementation Using FPGAs
1.3.1 Era of Early Logic Families
1.3.2 Era of LSI and VLSI Components
1.3.4 Era of Programmable Logic
1.4.3 The Configurable Hardware Paradigm
1.5.3 Technology-independent Design
1.5.4 The Mead–Conway Design Method
2. REVIEW OF LOGIC DESIGN AND ELECTRICAL ASPECTS
2.1 Combinational Circuit Design
2.1.2 Multiplexers and Boolean Function Evaluation
2.3.2 “One-hot” State Machines
2.4 Petri Nets for State Machines*
2.4.3 Extended Petri Nets for Parallel Controllers
2.4.4 Simple Example—A Traffic Light Controller
2.4.5 Implementation of Petri Net Description
2.5.1 Complementary MOS Circuits
2.5.2 Voltage Levels and Loading
2.5.4 Signal Propagation in CMOS
2.5.5 Electrostatic Precautions and ESD Protection
2.5.8 Metastability Characteristics
3. INTRODUCTION TO FPGA ARCHITECTURE
3.1 Background to the FPGA Concept
3.2 Channel-type Field-programmable Gate Arrays
3.2.1 Distinguishing Architectural Features
3.2.2 Scaling with Technology Improvements
3.3 Structured Programmable Array Logic
3.4 Computational Logic Arrays
3.5.2 Wide Gates and Long Lines
3.5.3 Switches and Switch Boxes
3.7.3 RAM- and Area-based Benchmarks
3.7.4 Benchmarking and Dynamic Reconfiguration
3.7.6 Summary and Health Warning
3.8.2 PALs and Structured PALs
3.8.5 VLSI Primitives and Programming
4. DESIGN PROCESS FLOWS AND SOFTWARE TOOLS
4.1.2 Tools for Design Validation
4.1.3 Tools for Physical Design
4.3.1 Conceptual Design of Display Driver
4.3.2 Design Verification of Display Driver
4.3.3 Physical Design of Display Driver
4.4 Design Process Flow: The Application-specific Integrated Circuit Route
4.4.1 Conceptual Design of Stopwatch
4.4.2 Design Verification of Stopwatch
4.4.3 Physical Design of Stopwatch
4.5 Libraries and Design Idioms
4.6 Placement, Routing, and Wireability
4.6.1 Rent’s Rule and Package Pin-outs
4.6.2 Rent’s Rule and Wireability
4.6.3 Partitioning Designs within and across Chips
5.3 Pseudorandom Number Generation
5.6.2 Serial Multiplier with Parallel Addition
5.7 A Parallel Controller Design*
5.7.1 Operation of Part of the Petri Net Controller
5.7.2 Characteristics of the Design Technique
5.7.3 Implementation on XC3090
6.2 Architecture of the CHS2×4
6.4 Self-timed First-In First-Out Buffer
6.4.3 Filling the Self-timed FIFO
6.4.5 A Full-custom Self-timed FIFO
6.5 Self-timed Genetic String Distance Evaluation
6.5.2 Genetic Sequence Comparison
6.5.3 Dynamic Programming Algorithm
6.5.4 Implementation Considerations
6.5.6 The Self-timed Implementation
6.6.3 Comparison with Previous Systems
6.7 Place-and-Route Acceleration
6.7.1 The Global Routing Algorithm
6.8 A Field-Programmable Gate Array for Systolic Computing
6.8.6 Absolute-difference Module and Accumulator
6.8.7 Processing-element Layout
7.1 Technology Push or Market Pull?
7.3 FPGA Market and Start-up Companies
7.3.5 Do You Need a Fabrication Facility?
7.4 The MPGA as an Alternative to the FPGA for Low-volume Production
7.5.3 The Semiconductor Chip Protection Act of 1984
7.6.1 Small Business Innovation Research
7.6.2 Small Business Technology Transfer Program
8.2.2 Pilkington (Motorola/Plessey/Toshiba)
8.3 Field-programmable Interconnect
8.3.1 Aptix Field-programmable Interconnect
8.3.2 I-Cube IQ160 Description