CMOS THz Wireline Communication 309
wave is excited and co nfined by the sub-wavelength SPPs T-line, re sulting in
much higher efficiency in restraining cro sstalk than the traditional T-line at
THz frequency with wider bandwidth. The insertion loss (S
21
) of both cou-
plers is further simulated as shown in Figur e 14.7(c). The proposed coupler
has 3 dB improvements in tr ansmission coefficient over the traditional coun-
terpart as frequency beyond 300 GHz. There is a valley in 270 GHz possibly
due to the resonances between meandering wires. Figure 14.7(d) shows the
simulated near-ended coupling (S
31
) remains lower than -10 dB for most fre-
quencies a cross wide-band, indicating low near-ended coupling. No te that in
this design, the line spacing is 2.4 µm with an attempt only to show the gr eat
advantages by the proposed SPP T-line. During the circuit design phase this
spacing is not necessary to be so narrow.
Recent state-of-the-art o n-chip implementations of interconnects using
conventional tr ansmission lines exhibit gre at attenuation and c rosstalk at high
frequency, w hich in turn demands more complex equalization techniques that
consume considerably more power and silicon area. For instance, Ref [305]
reported an interconnect model by assuming the Manhattan routing style
in 0.18-µm CMOS technology. This model employs metal 5 as the intercon-
nect to construct a B US with 10-mm length onto a lossy substrate. It shows
that, due to strong coupling b etween adjacent conductors the transfer func-
tion |H| drops to below -150 dB for all loadings at frequenc ies hig he r than
100 GHz, inhibiting most applications of THz on-chip communications. At
the same time, the crosstalk in multi-channel series link is quantized in Ref
[306] for a 10-mm interconnect in 0.13 µm CMOS, in which both the ad-
jacent cros stalk-to-signal ratio (ACSR) and distant crosstalk-to-signal ratio
(DCSR) dramatically increase as frequency goes up. This tendency is appar-
ently caused by the coupling capacitance that is inversely proportional to the
spacing. All of the above observations again confirm the significant crosstalk
induced by TEM mode propagation along the long T-line. While the lower-
layer metals can partially alleviate the crosstalk (the thickness of lower-layer
metals are over 2–3 times smaller than that of the top copper metal, and
the resulting coupling capacitance is reduced), the resistive loss will be pro-
portionally highe r. Similar ly, even though the crosstalk can be much reduced
by increa sing the distance a mong wirings, in order to support ultrahigh ag-
grega te bandwidth between modules/chips, silicon carrier channels must have
very high wiring density. Consequently, fine-pitch carrier wiring is required.
These wiring dimensions normally res ult in s ignificant resistive losses when
the on-carrier channel is long, e .g., over 5 mm [307]. Furthermore, as in the
case of commonly used backplane channels [308], silicon carrier channels have
very limited channel bandwidth, so the silicon carrier channel presents higher
losses at higher frequencies. As a result, when high-frequency data is transmit-
ted over long carrier channels, channel losses and limited channel bandwidth
make the recovery of received data difficult. In sum, all these studies have
shown great difficulty of efficiently realiz ing ultra-high speed on-chip da ta
transmission by conventional T-line.
310 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
To overcome all these fundamental limits by conventional transmission line
in THz frequencies, an on-chip surface plasmon polarito n (SPP) T-line with
sub-wavelength comb-shape onto the metal strip is demonstrated in sub-THz
region by CMOS technology. T he dispersion characteristics and field distribu-
tion are investigated from the design perspective toward on-chip THz commu-
nication. It shows that such a structure can tightly confine the surface wave
at the metal/dielectric interface, resulting in less loss a nd small crosstalk. A
SPP-based coupler is further fabricated in standard 65 nm CMOS with great
improvement on crosstalk reduction with wide-ba nd for on-chip interconnec-
tion. Measurement results show that the SPP coupler can guide the surface
wave with lower than -15 dB reflection coefficient and the cros stalk improve-
ment is on average 19 dB across 220 ∼ 325 GHz, w hich leads to nearly 3
dB lower transmission loss compared to the traditional T-line-based design.
Therefore, such a SPP T-line is very promising in highly dense on-chip co m-
munication at THz in CMOS technology.
To verify the above design observations, a SPP-based coupler was fabri-
cated by 1P9M bulk 65 nm CMOS process with the die micrograph shown
in Figure 1 4.6 (d). The area occupation is 400 µm × 225 µm. Due to limited
area, the c oupler is designed with a meandering s hape s uch that the equiva-
lent physical length of the coupler is approximated 2 mm to provide a long
coupling length. The spacing between the two SPP T-line is 2.4 µm which is
the minimum metal gap allowed by the design rule. Such a close spacing is
supposed to create a strong coupling for the long coupler, which would pro-
vide us a straight insight to evaluate the crosstalk reduction by the propos ed
structure. The topmos t copper layer (Metal 8) with thickness of 3.3 µm is ex-
clusively employed for the design as a low-loss coupler, and the top aluminum
layer (Metal 9) with 1.325 µm thicknesses is used to form the Ground-Signa l-
Ground (GSG) Pad which ha s measured characteristic impedance around 50
Ω across the 220 ∼ 3 25 GHz frequency range. Note that the thickness of
metal has very limited influence on the dispersion relation of SPPs because
the sub-wavelength na ture still maintains (the H -field remains unquantized
in the x direction.) [169], while the resistive loss c an be much improved for a
thicker metal. It is important to know that for the SPP T-line the resistive
loss cannot be reduced by realizing better confinement. Two terminals o f the
coupler are dir ectly connected to the signal trace of Pads and the other two
parts are termina ted by P+ while the resistive loss can be much improved for
a thicker metal. It is important to know that for the SPP T-line the resistive
loss cannot be reduced by realizing better confinement. Two terminals o f the
coupler are dir ectly connected to the signal trace of Pads and the other two
ports are terminated by P+ polysilicon resistors that were simulated having
50 ω impedances around 300 GHz. A lumped-e lement model was created to
fit the measurement result of Pad over wide-band, which is also an importa nt
part of the co upler design. Considering the Pad as part of the design, the
SPP-based coupler is designed and optimized for the best crosstalk reduction
before fabrication. The fabricated on-chip SPP-bas ed coupler has the follow-
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