150 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
reduced s ize and loss. In the following section, the feature of SEDFDA would
be revie wed first followed by detailed analys is for on-chip implementation
toward PA design.
7.3 PA Design with Power Combining Network
7.3.1 SEDFDA-Based PA Design
7.3.1.1 Review of SEDFDA
Wide ba ndwidth is usually achieved by distributed amplification in the mm-
wave region. One major limitation for traditional distributed PA is its low
PAE. As shown in Figure 7.2(a), each transistor outputs different power; there-
fore the transistors cannot be optimized simultaneously [7]. The power wasted
in the resistive terminations further degrades the efficiency. Both tra nsmission-
line and transistor sizes a re tapered in [7 ] to r ealize the maximized output
voltage swing at all distributed stage s (Figure 7.2(b)). Although each tran-
sistor still outputs different power, the same voltage swings are maintained
due to scaled transistor sizes. However, the large scaling ratio between transis-
tor stages limits the achievable number of distributed stage s and thus output
power. Furthermore, resistive terminations still c onsume power and degrade
efficiency. A new distributed amplifier called the dual-fed distributed ampli-
fier (DFDA) was pr oposed in [8], which can significantly improve the PAE
limitation for distributed PAs. As shown in Figure 7.2(c), the input signal is
split into 2 paths and fed into both ends of the gate line. The two outputs
from the drain line are then combined again as the output signal. It has been
proven that when a phase-shift of ±nπ (n=0,1,2...) is maintained between
transistors in both gate and drain lines, all transistors can see the same load,
and output the same power [200]. As a result, they can be optimized simul-
taneously. Moreover, the resistive terminations a re eliminated in DFDA, and
there is no additional power wasted. As a result, the PAE limitation of dis-
tributed PAs c an be resolved fundamentally. DFDA is further developed in
[9] as single-ended to eliminate the need of hybrid. The resulted topology is
shown in Figure 7.2(d), which is called the single-ended dual-fed distributed
amplifier (SEDFDA). Both input and output signals propagate to the open-
circuit ends and are reflected back. Since both forward and reflected signa ls
add up to each other under certain phase-shift of the T-line, the power gain
is further improved.
Note that both DFDA and SEDFDA require a phas e-shift of ±nπ
(n=0,1,2...) to be maintained between transistors in both gate and drain lines.
Since zero-phase-shift (n=0) is impossible to be realized by the traditional
T-line (which introduces phase-shift proportional to the T- line length), λ/ 2
T-line is used at PCB level to fulfill the phase-shift requirement, which is
however too bulky and lossy for on-chip implementation. One type of meta-
material called comp osite right/left-handed (CRLH) T-line can be used to
Power Combiner 151
(a)
(b)
(c)
(d)
Figure 7.2: Distributed amplifier (DA) topologies: (a) conventional
DA, (b) tapered DA [7], (c) DFDA [8], (d) SEDFDA [9].
realize a real zero-phase-shift, and is implemented for distributed amplifier
design in [200] and [201] at the PCB level for GHz region applications. How-
ever, at this frequency region, CRLH T-line is too bulky and lossy for on-chip
implementation in CMOS technology.
With frequency pushed into the mm-wave frequency region, such as 60GHz,
the lumped capacito r and inductor to build CRLH T-line structures are more
compact and less lossy and hence feasible for on-chip implementation in CMOS
technology. In this chapter, CRLH T-line-based ZPS is studied for the first
time in on-chip power amplifier desig n at 60GHz [202]. Detailed design consid-
erations are studied for ZPS to achieve low loss and wide-band performance
for 60GHz PA applications.
Both DFDA and SEDFDA have been analyzed in [200] and [203] but
targeted for PCB design at the GHz level, where T-lines are normally assumed
ideal. For on- chip power amplifier design at 60GHz and beyond, T-lines are
no longer ideal and the amplifier p erformance ca n be greatly affected. In the
following, we present the design analysis background of SEDFDA, and then
show the design implicatio ns when considering the non-ideal T-line targeted
for on-chip 60GHz applications.
7.3.1.2 SEDFDA Performance Analysis under Ideal T-Line Model
Figure 7.3 s hows the equivalent circuit for one N -stage SEDFDA. The upper
half is the gate line and the lowe r half the drain line. All parasitic components
152 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 7.3: Equivalent circuit for single-ended dual-fe d distributed
amplifier (SEDFDA).
from trans istors can be absorbed into the T-line model. Resulted T-lines for
each section in both gate and drain pa ths are then characterized with char-
acteristic impedance Z
g
/Z
d
, propagation constant γ
g
/γ
d
, and physical length
l
g
/l
d
. The input impedance and load impedance are termed as Z
S
and Z
L
.
Perfect open circuits are assumed for terminations on both gate and drain
lines. The input signal travels along the gate line, meets open-circuit termina-
tion, and is reflected back ag ain. Forward and backward signals add together
to form transistor gate voltage V
gk
(for the k-th distributed stage), which c on-
trols the corresponding drain curre nt I
dk
. Assume n
S
=Z
g
, gate voltages for
all transistors can be calculated by directly adding the forward and backward
voltages:
V
gk
= V
in
[e
−kγ
g
l
g
+ e
−(2N−k)γ
g
l
g
]. (7.1)
One special property for a distributed amplifier is that transistor drain
voltage (V
dk
) is affected by all transistor drain currents. Assume Z
L
=Z
d
, with
a similar method as [200], all drain voltages for SEDFDA can be ca lculated:
V
dk
=
g
m
V
in
Z
d
(A1+A2+B1+B2)
1 + coth [(N − k) γl
d
]
(7.2)
where A1, A2, B1 , B 2 are:
A1 = e
−kγ
g
l
g
× e
−k(γ
d
l
d
−γ
g
l
g
)/2
×
sinh[(k−1)(γ
d
l
d
−γ
g
l
g
)/2]
sinh[(γ
d
l
d
−γ
g
l
g
)/2]
,
A2 = e
−(2N−k)γ
g
l
g
× e
−k(γ
d
l
d
+γ
g
l
g
)/2
×
sinh[(k−1)(γ
d
l
d
+γ
g
l
g
)/2]
sinh[(γ
d
l
d
+γ
g
l
g
)/2]
,
B1 = e
−kγ
g
l
g
× e
−(N−k)(γ
d
l
d
+γ
g
l
g
)/2
×
sinh[(N−k+1)(γ
d
l
d
+γ
g
l
g
)/2]
sinh[(γ
d
l
d
+γ
g
l
g
)/2]
,
B2 = e
−(2N−k)γ
g
l
g
× e
−(N−k)(γ
d
l
d
−γ
g
l
g
)/2
×
sinh[(N−k+1)(γ
d
l
d
−γ
g
l
g
)/2]
sinh[(γ
d
l
d
−γ
g
l
g
)/2]
.
(7.3)
The load line impedance for all tr ansistors can then be obtained:
Z
dk
=
V
dk
I
dk
=
V
dk
g
m
V
gk
. (7.4)
Power Combiner 153
If the same load line impedance can be maintained for all transis tors, their
power performance can be optimized simultaneously. For lossless T-line as
in the case for GHz region applications at PCB level, it can be achieved by
maintaining a same phase shift ±nπ (n=0,1,2...) of both gate and drain line s:
Z
dk
= N Z
d
when β
d
l
d
= β
g
l
g
= ±nπ (n = 0, 1, 2 . . .) (7.5)
where β
g
and β
d
are the phase c onstants for T -lines on gate and drain paths,
respectively. In this case, all transistors ca n be fully utilized, a nd efficiency of
the whole amplifier depends on that of each transistor. For example, for class-
A amplifier design, the optimized efficiency can be achieved by implementing:
Z
dk
= (V
max
− V
min
)/I
max
, where V
max
and V
min
are the maximum and
minimum output voltage for class A operation and I
eax
is the maximum output
current.
The improvement in efficiency c an also be observed through the improve-
ment in power gain. With (7.5) satisfied, the power gain can be calculated
as:
Gain =
P
out
P
in
= 4N
2
g
2
m
Z
g
Z
d
(7.6)
which is 16 times larger than the conventio nal distributed amplifier with the
same number (N ) of transistors.
However, for on-chip distributed amplifier design at 60GHz and beyond,
T-lines can no longer be assumed as ideal. Large paras itic components of tran-
sistors which are absorbed into the T-line design further degrade its perfor-
mance. Both loss and phase error on the T-line can severely degrade amplifier
performance, and therefore should be taken into consideration with detailed
analysis as shown below.
7.3.1.3 Effect of T-Line Loss on SEDFDA
As frequency pushes up into the mm-wave region and transistor size shrinks
down to below 100nm, the lossy substrate, thin metal layer, and strong cou-
pling between them severely degrades the quality factor of passive components.
What is worse, the large a nd low-Q parasitics of the transistor, which a re ab-
sorbed into the T-line design, can severely degrade the effective Q-factor of
T-line. For a prac tical on-chip amplifier such as the PA design at 60GHz, loss
on T-line must be taken into consideration.
Recall that (7.5) and (7.6) assumed ideal T-lines in both gate and drain
paths, i.e., where α
g
and α
d
are the attenuation constants for T-lines on gate
and drain paths, respectively. For the practical on-chip design, α
A
and α
d
can
no longer be assumed zero and are used to represent the loss on T-line. As a
result, the conclus ion in (7.6) ca n be affected.
The impact of T-line loss to the SEDFDA design is further illustrated
by one simulation example. Figure 7.4 shows the impact of T-line loss on
SEDFDA power gain. Here g
m
is assumed to be 20mS and characteristic
impedance on both g ate and drain lines a re set as 50ω. Loss per distributed
154 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
(a)
(b)
Figure 7 .4: Effect of T-line loss on SEDFDA performance.
stage on T-lines are defined as α
g
l
g
(α
d
l
d
) and assumed identical on both
gate and drain paths. As Figure 7.4(e) shows, loss on the T-line severely
degrades the power gain in an exponential manner. For example, for a 10-
stage SEDFDA, the power gain reduces from above 25dB to below 0dB as los s
on the T-line increases from 0dB/stage to 2dB/stage. It can also be observed
that the impact o f loss on power gain becomes more severe as the number of
stages (N ) increases. This can be understood because as N increases the signal
needs to pro pagate through more lossy stages to the output and therefore it
experiences more degradation. As a result, there exists an optimum N for a
sp ecific value of loss in order to achieve the highest power ga in. This optimum
N decreases as loss per stage increases. In other words, loss on the T-line limits
the maximum numbe r of stages that can be implemented in the SEDFDA.
The advantage of SEDFDA over the conventional distributed amplifier
is its improvement on power gain and efficiency. As (7.6) shows, an ideal
SEDFDA can improve power gain by 12dB, and improves the efficiency pro-
portionally. However, as loss in T-line increases, this advantage gradually di-
minishes. Figure 7.4(b) shows the impact of T-line loss on the power gain
improvement, which is calculated by dividing the obtaine d power gain by the
power gain of a conventional distributed amplifier with the same number of
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