Power Combiner 183
Figure 7.32: The measured S parameters of PA and its stability factor
with center frequency (63 GHz) under 1 V supply.
7.4.3.1 60GHz PA Design
The desig ne d differential CRLH T-line-bas ed ZPSs implemented in both gate
and drain lines are shown in Figure 7.34, with the parasitic capacitances from
transistor late and drain absorbed in ZPS design. The designed C RLH T-lines
can re alize zero-phase shift at 60GHz with co mpact size of 49µm×76µm and
50µm×72µm in gate and drain lines, respectively.
Figure 7.35 further compares the performance between zero-phase CRLH
T-line and traditional RH λ/2 T-line with transistor parasitic capa citance and
loss abso rbed into the design. As the top figure shows, as freque nc y changes,
the phase shift in zero-phase CRLH T-line var ies much slowe r than λ/2 T-
line. For example, a phase change within ±10
◦
can be maintained in the 14
GHz frequency range (53 to 67 GHz) in the designed zero-phase CRLH T-line,
while in λ/2 T-line it can only be maintained in the 4.5 GHz range (57.5 to
62GHz). In other words, zero-phase CRTH T-line can provide a much wider
band performance than λ/2 T-line. The insertion loss is also compa red in the
lower figure. By absorbing parasitic capacitance and loss fr om trans istor, the
zero-phase CRLH T-lines show insertion loss be low 0.9 dB and 1.4 dB in 50
GHz to 70 GHz frequency r ange in the gate line and drain line, respectively,
184 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 7.33: The measured output power and PAE of PA at center
frequency (63 GHz) under 1 V supply.
Figure 7.34: On-chi p implementation of CRLH T-line (metamaterial)
to realize zero-phase shift in standard CMOS technology for the 60
GHz PA prototype with differential 4×4 distributed power combining
network.
Power Combiner 185
Figure 7 .35: EM simulation results of both loaded CRLH T-lin e and
loaded λ/2 T-line for comparison. Slower S21 phase change of CRLH
T-line indicates wider bandwidth, while the dB(S21) p lot indicates
lower loss. The dB(S11) plot shows wideband matching.
while λ/2 T -line contributes more than 3dB loss in both gate and drain lines.
In conclusion, the implemented on-chip differe ntial zero-phase CRLH T-line
demonstrates much more co mpact size, wider bandwidth and lower loss than
λ/2 T-line.
The PA implementation is shown in Figure 7.36 with 3 stages and 58
GHz as the central frequency. The first 2 stages work as drivers; and a 4×4
distributed power combining array is in the 3
rd
stage, which has 4 power-
combining branches with each branch be ing a differential 2-stage distributed
PA. Same transistor topology, size and biasing are adopted. As 4 branches are
combined in parallel at the output instead of 2 branches, matching to 50Ω at
186 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 7.36: Schematic of the 60 -GHz PA prototype with 3 stages and
differential 4×4 distributed power combining network at 3
rd
stage.
the output node would require 200Ω in each branch, which cannot be provided
by in-chip T-line. As a result, signal distribution lines are absorbe d into the
output matching network, which re duces the PA bandwidth due to its long
length.
Neutralization technique is used to boost the PA’s performa nc e while en-
suring stability. The risk of mismatch and performance degra dation due to
sensitivity of the neutralization capacitor to process variation is minimized by
adopting multiple larg e-value c apacitors connected in serial. Since the capac-
itance o f each capacitor is much larger than a single neutralization capacitor,
its sensitivity to variation can be reduced.
Power Combiner 187
Figure 7.37: Simulated voltage swings on both distributed stages in
the gate line and drain line of designed 2D distributed power com-
biner. Similar voltage magnitude indicates simultaneous power opti-
mization for each transistor, while similar ph ase indicates in-phase
power combining.
The digital control system is integrated for this PA implementation to
facilitate power back-off with enhanced efficiency. The system view for the
digital control loop is shown in Figure 7.19, where the output power level
is sense d by a power coupler and converted to DC signal throug h a power
detector. T he detected signal is further converted to digital sig nal through
a 3-bit ADC and passed to off-chip signal processing. The feedback digital
signal is then converted to analog signal through a 3-bit DAC to control PA’s
biasing. The capacitive power coupler designed in Figure 7.16 is selected to
minimize the effect of power detection on PA’s output power performance. The
single-ended square law power detecto r designed in Figure 7 .18 is adopted to
fit the single-ended PA output.
7.4.3.2 Simulation and Measurement Results
Simulation Results
Figure 7.37 shows simulated voltage swings on the transistor gate and drain of
both distributed stag es of the implemented differential 2D power combining
network at 60GHz. As the figure shows, both gate and drain voltage swings
have almost the same phase and a mplitude in two distributed stages. As a
result, the power performance of transistors in distributed amplifier can be
optimized simultaneously and in-phase combined in series, thus improving
the power ga in and efficiency of the whole distr ibuted amplifier.
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