114 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 5.8: Measured and simulated output power and power effi-
ciency of proposed VCO over entire 60 GHz band.
by switching the inductive loadings from Sa and Sb. The entire 60-GHz band
under the IEEE 802.15.3c standard is completely covered in both simulation
and measurement. Note that the measured FTR of pro posed VCO is 15.8%
from 58.1 to 68.1 GHz, which is slightly lower than the simulation result
of 16.8% from 58.4 GHz to 69.1 GHz. Figure 5.10 shows the measur ed and
simulated phase noise a t 60 GHz output frequency. The mea sured phase noise
correlates very well with the simulation results. A -116.7 -dBc/Hz phase noise
is observed at 10-MHz offset, which is about 2.5-dB lower than the simulation
result at the same frequency offset.
The performance of the proposed VCO is summarized in Table 5.1 with
compariso n of other similar desig ns at 60 GHz. It can be observed that the
proposed design has the highest output power of +3 dBm, the highest power
efficiency of 2.2% and the wide st FTR of 15.8%. Note that the phase noise of
the pr oposed VCO is very clo se to the best re ported result of -118.8 dBc /Hz
at 10-MHz offset in [174]. However, the output power of the proposed VCO
is almost 10 times (9.6-dB) higher. This lea ds to the state-of-the-art figure of
merit (FOM) and figure of merit with tuning range (FOMt) as well, which are
defined by the fo llowing equations:
(
F OM = P N(∆f) − 20log(
f
osc
∆f
) + 10log(
P
diss
1mW
)
F OMt = P N(∆f) − 20log(
f
osc
∆f
×
F T R
10
) + 10log(
P
diss
1mW
)
(5.11)
where PN(∆f) is the phase noise at the o ffset frequency ∆f, f
osc
is the oscil-
lation frequency and P
diss
is the DC power consumption in mW. The highest
output power and lowest phase noise both confirm the feasibility of applying
the proposed ZPC in mm-wave IC designs. The maximum power density of
Coupled Oscillator Network 115
Figure 5.9: Measured and simulated VCO FTR under various switch
configurations to cover 58.3–64.8 GHz continuously.
the proposed VCO is 18.4 mW/mm
2
, which is more than 8 times higher than
the pre vious VCO design in [174]. Note that power density is defined as the
output power generated in unit chip area (P
OU T
/A
CORE
).
Figure 5 .10: Measured and si mulated VCO phase noise at 60 GHz.
116 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Table 5.1: Performance Comparison of State-of-the-Art VCO Designs
around 60 GHz
Parameters
[162] [154] [77] [174] This Work
Technology
0.13-µm
CMOS
32-nm
CMOS SOI
65-nm
CMOS
90-nm
CMOS
65-nm
CMOS
f
osc
(GHz)
56.5 102.2 40 57 63.1
FTR (%)
10.3 4.1 10.5 14.3 15.8
Phase Noise
@10MHz
(dBc/Hz)
−108
@10M
−100.8
@10M
−85 @10M −118.8
@10M
−116.7
@10M
Output Power
(dBm)
−18 −30.7 −13 −6.6 +3
Power Efficiency
(%)
<0.16 0.013 <0.1 1.5 2.2
FOM (dBc/Hz)
−173.1 −172.45 −162 −184.3 −172.9
FOM
t
(dBc/Hz)
−173.4 −164.75 −162.4 −187.4 −177.3
A
CORE
(mm
2
)
0.06 0.0014 — 0.1 0.11
P
OUT
/A
CORE
(mw/mm
2
)
0.26 0.6 — 2.2 18.4
5.3.2 140 GHz CON Signal Source
Figure 5.11 shows the block diagram of the proposed 140-GHz signal s ource, of
which the core is a 70-GHz CON with four zero-phase-coupled oscillator unit-
cells. Since the output signals after frequency doublers are still in-phase, they
are directly combined at the center of CON to generate a four times higher
output power. The oscillation frequency of CON is controlled by the injection
locking method. Compared to the direct frequency control by a 70-GHz phase
lock loop (PLL) with the bulky and power hungry frequency dividers, the
injection lo cking method has higher power and area efficiency. In this work,
the 70-GHz injection s ignal is obtained by doubling the fre quency of a 35-GHz
reference input, which can be easily generated by an on-chip or off-chip signal
generator. The design of each circuit block is shown in the following section.
5.3.2.1 Zero-Phase Oscillator Unit-Cell at 70GHz
Figure 5.12 shows the schematic and layout of an on-chip MPW-based oscil-
lator unit-c ell with coupled T-line implemented in the topmost copp er layer
(M8) and parasitic capac itances fr om transistor s in the 65-nm CMOS pro-
cess. Here an inter-digital coupling topology is deployed to largely incre ase
the magnetic coupling inside each unit-c ell. Both input and output of the
unit-cell are on the same side due to the dumbbell-shaped routing with an ef-
fective length of 40 µm. Switch-controlled inductive loadings by Sa and Sb are
applied to increase the number of the available zero-phase modes of unit-c ell
as well as the tuning range of CON. The unit-cell EM-simulation results and
Coupled Oscillator Network 117
Figure 5.11: Block diag ram of proposed 140 GHz signal source with
center combined output from four 70 GHz zero-phase-coupled oscil-
lator unit-cells.
the dispersion diagram extracted by the method introduced in [175] without
any inductive loadings are shown in Figure 5.13 and 5.14, respectively, where
a very small insertion loss of 0.4dB is observed in zero-phase mode at 70 GHz.
Note that a parasitic c apacitance of 40fF from active devices is also consider ed
in the simulation. Moreover, the metamaterial properties of proposed on-chip
unit-cell design are verified by a similar dispersion diagram to Figure 2.2.1.5
except the loss-induced non-zero α at zero-phas e mode.
5.3.2.2 70GHz Zero-Phase Coupled Oscillator Network
The schematic of the 70-GHz CON is shown in Figure 5.15. Four MPW-
based oscillator unit-cells are serially connected in a closed-loop form. Due
to the strong in-phase inductive coupling inside each zero-phase oscillator
unit-cell, the differential output sig nals at locations A, B, C and D have the
same phase, magnitude and frequency, which are locked to the injected 70-
GHz reference signal with largely amplified strength. The oscillation signal is
generated by compensating the energy loss in each unit-cell with a negative
resistance formed by cross-coupled NMOS pair (M1 and M2). Usually larger
M1 and M2 are preferred to ensure the os cillation condition, but the availa ble
output power will be correspo ndingly reduced. Additionally, in order to reduce
the impacts of the pr ocess variation, a central symmetrical layout is deployed
and all active devices are placed as close as possible to the geometrical center
of CON.
118 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 5 .12: Schematic of on-chip ZPC-based oscillator unit-cell at
70-GHz band with inter-digital coupled T-line and switch-controlled
inductive loadings.
5.3.2.3 70GHz to 140GHz Output Frequency Doublers
Figure 5.16 shows the schematic of four 70-GHz to 140-GHz push-push fre -
quency doublers with center combined output. The 70-GHz differential output
signals at A, B, C and D are coupled to the push-push frequency doubler by
28fF DC-block capacito rs. Therefore, all the frequency doublers can be e xter-
nally biased to the threshold le vel (VG1) to maximize the frequency conversion
efficiency. The resulting four in-phase 1 40-GHz output signals are directly tied
together to generate a high power output signal at the center with a combined
output impedance of 50 Ω. Moreover, a LC resonator-based AC-GND is ap-
plied to reduce the output leakage of the 70-GHz fundamental signal. A CPW
T-line with 210-µm length and 50-Ω characteristic impedance is us ed to con-
nect the center output to the RF PADs. The cross-section of CPW T-line is
also shown in in Figure 5.16. According to the EM-Simulation at 140 GHz,
the CPW T- line has an insertion loss and Q-factor (Q) of 0.45 dB and 1 3.5,
respectively.
5.3.2.4 35-GHz to 70-GHz Input Reference Frequency Doubler
Figure 5.17 shows the schematic of the 35-GHz to 70-GHz Reference Frequency
Doubler. One trans former-based ba lun is deployed to gene rate a differential
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