Coupled Oscillator Network 109
Figure 5.2: The calculated l for zero coupl ing phase vs. loaded capac-
itance and even-mode characteristic admittance at 60 GHz.
5.3 Circuit Prototyping and Measurement
5.3.1 60 GHz CON Signal Source
5.3.1.1 Differential ZPC Unit-Cell
Figure 5.3 s hows the schematic and layout to implement a differential ZPC
by the topmost copper layers (M5, M6) and aluminum layer (AL) with inter-
digital coupling topology in 65-nm CMOS process. The average length of
the coupler is 18 2µm. The sizes of transistors are pre-determined by the re-
quired output power and the frequency range. Their parasitic capac itances
are extracted from post-layout simulation as the load of one ZPC. These ca-
pacitances are then incorporated into the EM simulation to satisfy (5.6). The
design satisfies the zero-pha se condition at 60GHz as illustrated in Figure 5.4.
In addition, the S11 is smaller than -20 dB and the differential S21 is greater
than -0.5 dB at the vicinity of 60 GHz, which confirm a low co upling loss.
As a comparison, a conventional coupler using two coupled T-lines with the
minimum allowed gap (1.5 µm) is also simulated. With the same c apacitance
load (40 fF), the proposed ZPC obtains 2-dB better S21, leading to a lower
coupling los s. The propagation constant of the proposed ZPC as illustrated
in Figure 5.5. β is negative before 60 GHz, which presents the left-handed
property. A zero β is achieved at 60 GHz leading to the zero-phase coupling
condition. At the same time, the attenuation constant α is also minimized at
around 60 GHz, re sulting in the minimum coupling loss. As shown in Figure
110 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
-gm
-gm
-gm
-gm
I
+
I
-
I
+
I
-
Vtune
Vtune
Vtune
Vtune
Vout+
Vout-
I
in
32 x 4um(x4)
20x1.7um (x8)
2x1um
M1
M2
M3
M4
-gm
ZPC
ZPC
ZPC
ZPC
CPW 120 µm
µm
CPW 120
w
M6
w w
s
s
w = 6 µm;
s = 4 µm.
Figure 5.3: Layout of inter-digital differential ZPC with effective elec-
trical length controlled by MOS switches.
5.5, the negative relative permittivity (ε
r
) realized by the CMOS on-chip ZPC
confirms the metamaterial characteristic.
Figure 5.4: Simulated magnitude of S11 and S21 in dB and phase
of S2 1 of the proposed coupler structure with comparison of S21
magnitude to the conventional one by coupled T-li ne.
Coupled Oscillator Network 111
Figure 5.5: The extracted dispersion diagram and relative permittiv-
ity (ε
r
).
5.3.1.2 ZPC-Based Oscillator with Tuning
Since a broadband zero coupling phase is desired, based on (5.6) and (5.7) the
frequency tuning can also be achieved by changing the effective length of the
coupler. The inductive loading method [170] is applied to achieve the wide
tuning range. Two metal loops are formed above the coupler in the aluminum
PAD layer (LB). By configuring the on-off status of MOS switches M
a1,2
and
M
b1,2
shown in Figure 5.3, the effective electrical length of the coupler is
changed, which in turn changes ZPC oscillator frequency as shown below
ω
0,mn
=
1
p
C
eq
(L
eq
+ mM
A
+ nM
B
)
(5.9)
where C
eq
L
eq
defines the maximum operation frequency; m = 0, 1, n = 0, 1
denotes the modes of configurations; M
A
and M
B
are the loaded mutual
inductances. As such, the minimum FTR without considering varactor tuning
can be calculated by
F T R = 2
ω
0,00
− ω
0,11
ω
0,00
+ ω
0,11
. (5.10)
In order to achieve higher FTR, larger M
A
and M
B
are required.
The loa ding capacitance is contributed by the parasitic of the cross-coupled
NMOS pair (M
1
and M
2
), output buffers (M
3
and M
4
) and va ractors (D
1
and
D
2
). M
1
and M
2
provide a negative resistance to compensate the energy los s.
The sizes of M
1
and M
2
are optimized with the maximum tuning range. The
drain-source current of cross-coupled pair is controlled by a ta il current con-
nected NMOS M
5
, of which the biasing can be adjusted. To facilitate output
112 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
-gm
-gm
-gm
-gm
I
+
I
-
I
+
I
-
Vtune
Vtune
Vtune
Vtune
Vout+
Vout-
I
in
32 x 4um(x4)
20x1.7um (x8)
2x1um
M1
M2
M3
M4
-gm
ZPC
ZPC
ZPC
ZPC
CPW 120
CPW 120 µm
µm
w
M6
w w
s
s
w = 6 µm;
s = 4 µm.
Figure 5.6: Schematic of proposed VCO with differential outputs com-
bined at the center.
impedance matching and isola te the VCO core from pe ripherals, commo n
source NMOS M
3
, M
4
are employed as output buffers. The width of M
3
, M
4
are optimized for high output power.
5.3.1.3 60-GHz Zero-Phase-Coupled Oscillator Network
The s chematic of the distributed zero-phase-coupled VCO network is shown
in Figure 5.6 . Four differential ZPC unit-cells are connected in serial w ith a
closed-loop. T he ir power outputs are combined at the geometry center of the
layout. A CPW T-line with 120 µm length and 50 Ω characteris tic impedance
is use d to connect the center output to the RF PADs. The cro ss-section of
CPW T-line is a lso shown in in Figure 5.6. According to the EM-Simulation
at 60 GHz, the CP W T-line has an insertion loss and Q-factor (Q) of 0.1 dB
and 15, respectively. Note that all the tail c urrents of all oscillator unit-cells
are controlled by the same current mirror with diode-connected NMOS.
5.3.1.4 Measurements
As shown in Figure 5.7, the distributed 4-way ZP C -based CON was fabri-
cated in the UMC 65-nm CMOS process w ith f
T
/f
MAX
of 170/190 GHz.
The cor e chip area is 330µm×320µm excluding Pads. It was measured on
CASCADE Microtech Elite-300 probe station and Agilent PNA-X (N5247A),
E5052 source signal analyzer with s pectrum s wept up to 7 0 GHz. Bias-T,
probe and cable loss are calibrated before the measurements. The proposed
VCO consumes 91-mW DC power under 1.2-V powe r supply. Note that the
Coupled Oscillator Network 113
Out+
Out–
Figure 5.7: Die micrograph of the fabricated 60 GHz VCO chip in 65
nm CMOS.
differential outputs are on different sides of the chip. Since the mea surement
is performed at single-ended RF output with GSG Pads, +3 dB is added to
the output power level. In addition, the simulation res ults are obtained from
Cadence Spectre post-layout s imulation.
Figure 5.8 shows the simulated and measure d output power of VCO in
each mode. Similar to the simulation results, the measured output power of
VCO is highest when Sa = 1.2 V and Sb = 1.2 V. This is mainly due to
a higher trans conductance of NMOS transistors at a lower frequency. The
proposed VCO achieves the highest output power of 2 mW (3 dBm) at V
T une
= 0 condition, where the oscilla tion frequency is 58.1 GHz. The corresponding
maximum DC-RF efficiency is 2.2%, which is defined by P
OU T
/P
DC
, where
P
OU T
and P
DC
are the output power and DC p ower consumption of VCO,
respectively. Figur e 5.9 shows four modes of VCO with different frequency
bands obtained from both simulation and measurement, which are generated
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