160 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
determined, which in turn determines the characteristic impedance of
the drain line (s
d
).
A balanced condition (ω
s
= ω
p
) is preferred for optimized ZPS p erfor-
mance, which leads to a characteristic impedance of Z
o
=
q
L
p
C
s
=
q
L
s
C
p
according to (). However, the actual parasitic reacta nc e from transistors
(L
s
’ and C
p
’) is unlikely to follow the above relation for L
s
and C
p
. As a
result, the s ize of L
t
or C
p
needs to be over-designed to generate wanted
i
d
. Ag ain, high loss and narrow bandwidth are caused for the designed
ZPS, which degrades PAE performance. In summary, PAE is affected by
both transistor DC bias and ZPS performance, and a compromise ne eds
to be made between these two parts.
3. The parallel combining topology not only affects P
out
/area and PAE
performances dir ectly through its efficiency, but also affects them indi-
rectly through the output matching. As stated in (7.5), with a fixed load
line impedance Z
dk
, the characteristic impedance for the drain line is
Z
d
= Z
dk
/N , where N is the distributed stages. Assuming M distributed
amplifiers (DAs) are combined in par allel, the output impedance can be
calculated as Z
out
= Z
dk
/(MN ) if the Z
d
for all DAs are combined in
parallel, which is the case for zero-degree power combiner.
Though the co mbiner has the benefit of merging part of the DA design
into itself with reduced loss, a large combining network (large MN ) may
lead to very small output imp edance and degrade the whole PA perfor-
mance. In this case , other combining topologies which can co mbine the
Z
d
for all DAs in serial may be used, which generates output impedance
of Z
out
= M Z
dk
/N instead, thus relaxing the stress on output matching.
This is the case for transformer combiners.
In summary, selections and design iterations may be made to choose the
most suitable power combining topology. Note that a zero- de gree tower com-
biner is selected for parallel combining in one single-ended PA pro totype with
a small 2×2 combining network; while transformers are further implemented
in differential PA prototypes with larger co mbining networks.
7.3.2.2 Differential Design
The afo rementioned 2D distributed power c ombining topology in Figure 7.8 is
implemented in single-ended manner. However, due to the single-ended topol-
ogy with a large matching network deployed, the benefit to achieve wide-band
high-density powe r combining is not fully demonstrated.
In this section, we introduce a differential 2D power combining network for
60GHz PA design in 65nm CMOS with further improved output power density.
Transformer matching and neutraliza tion capacitor are also deployed to enable
a larger power c ombining network with further improved PA pe rformance.
Power Combiner 161
Figure 7.9: Differential ve rsion of proposed SEDFDA PA topology
based on 2D distributed power combin ing network with the use of
CRLH ZPS s.
With the use of differential CRLH T-line-based ZPS des igned, one dif-
ferential 2D power combining network can be realized as shown in Figure
7.9, with benefits of re duced area due to merged parallel inductors and the
elimination of de-coupling capacitors. Moreover, loss is a lso reduced due to
confined EM field and nullified parasitic at v irtual ground in the differential
top ology. In a dditio n, the differential topology also allows easy implementa-
tion of techniques such as transformer matching and neutralization capacitor.
Transformer ma tching provides DC isolation with easy biasing and compact
area. Neutralization capa citor improves stabilization, simplifies matching, and
also boosts gain with minimized external loss.
There are, however, two design challenges for the proposed differ ential
top ology. First, for a differential implementation, it is desired to design the
circuit as symmetric as possible. An asymmetric implementation would cause
mismatch in the differential signals and degrade the pre-mentioned benefits.
However, since transistor pairs, differ ential ZPS, and differential input and
output terminals are all connected together, it is almost impossible to have a
fully symmetric implementation. Second, the input and output ter minals in
Figure 7.9 are on the same side of the power combining network. This would
162 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 7.10: The proposed layout for differential 2D power combining
network.
lead to long overlapped interconnection, which severely increases parasitics
and degrades performance.
To solve the above -mentioned problems, one novel differential 2D power
combining network is proposed in Figure 7.10. For each differential gate-line
and dra in-line, the differential ZPS is implemented in the first distributed
stage only. The differential signals then flow into separate directions to 2
single-ended ZPSs on both sides. In this way, the differential top ology can be
maintained highly symmetrical, while input and output terminals are placed
on opposite sides of the power combining network. Though some of the ZPSs
are re alized sing le-ended, the whole topo logy is still differential, allowing tech-
niques such as transformer matching and neutralization capacitor toward com-
pact matching and stabilization.
7.3.3 Stabilization Techniques
Stability is an imp ortant concern for all amplifier designs. Normally, additional
circuit components or special amplifier topologies are required which either
degrade PA’s performance or have more stringent system requirements. In
this section detailed analysis is provided for PA stabilization methods at mm-
wave frequencies and possible solutions to minimize the risk of instability while
maintaining PA performance from degradation.
Power Combiner 163
7.3.3.1 Common PA Stabilization Techniques
Neutralization
In the mm-wave region, parasitic capacitance between gate and drain ter-
minals of the transistor forms a feedback loop in common source amplifiers,
which degrades both power gain and stabilization. For differential topolog y, a
neutralization technique has been widely used recently [72, 204, 205, 206] to
neutralize the feedback signal by introducing a negative path from the drain
of one differential transistor to the gate of the other tr ansistor. As shown in
Figure 7.11, by introducing neutralization capacitor s C
neu
with s imilar ca-
pacitive coupling as the parasitic gate-drain capacitance C
gd
, the feedback
from the differe ntial outputs cancel each other, and the PA can therefore be
stabilized.
Neutralization technique is widely used recently for differential PA due
to several advantages. Firstly, the topology is very simple. Only two very
small capacitors are required with almost no layout overhead. Secondly, by
neutralization of the feedback from C
gd
, S12 of PA approaches 0. The amplifier
becomes near unilater al, thus making input and output matching independent
of each other, which greatly simplifies the matching process. Thirdly, C
neu
actually introduces a positive feedback loop. By properly choo sing C
neu
value,
in addition to achieving stabilization, the gain of PA can be slightly boosted.
However, the neutralization technique does have some limitations. Firstly,
this technique is sensitive to process variation because the PA is only stable
within a small region of C
neu
values. In fact, with a large C
neu
value the topol-
ogy shown in Figure 7.11 becomes a cross-coupled trans istor pair commonly
Figure 7 .11: Neutralization technique for PA stabilization.
164 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
used in VCO to generate a negative resistor. As a result, the PA becomes a
VCO. Secondly, due to additiona l capacitance loaded on the transistors, the
parasitic of transistors almost doubled. This effect is more significant for input
matching and for more advanced technolo gy, as the gate impedance locates
near the edge of Smith Chart, making the impedance matching narrow band.
Cascode
Cascode top ology is commonly used at lower frequency regions for stabiliza-
tion. It also helps to r educe the Miller effect from C
gd
and improve powe r
gain. In addition, cascade topology also shows o n adva ntage for advanced tech-
nology with low break-down voltages. Due to serial connection of transistor
junctions, a higher supply voltage can be used, thus increasing the achievable
output power. However, as frequenc y pushes higher, the large capacitance a t
the source of cascode transistor (C
gs
+C
gd
) would ca use performance degrada-
tion. A matching network such as a serial inductor L
s
can be added between
the cascode transistor and the common-source transistor [197, 207]. As shown
in Figure 7.12, the added inductor (L
s
) resonates out the two parasitic ca-
pacitors (C
gt
and C
gd
) by forming a low-pass filter. The penalty is additional
area and loss introduced by the serial inductor. A hybrid design is co mmonly
used where the previous stages are realized by cascode for stability and higher
gain, while the power combining stage is realized by common source to pol-
ogy for better efficie nc y [197], which however requires multiple supply voltage
levels. Nevertheles s, at 60GHz, normal casco de topology can still function
properly without inserted matching network, and is used to achieve a higher
Figure 7 .12: Cascode topology for PA stabilization.
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