218 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 9.4: Simulated Γ plot in Smith chart of SRR/T-line u nit cell
at resonance.
wave resonator as follows. Fir stly, the smaller size of the DTL-SRR leads to
a lower substrate loss, and hence the deno minator above decreases. Secondly,
for the DTL-SRR, the strong EM-energy coupling between the SRR and T-
line with perfect reflection can enha nc e the energy storage ca pability with the
nominator in (9.2) increased. Thereby, one can expect that a higher quality
factor can be achieved by DTL-SRR than the standing-wave resonator, which
is further validated by the measured experiment results.
9.3 Differential TL-CSRR Resonator
It is not feasible to directly deploy the etched CSRR from ground [78] on
chip due to the lossy substrate in CMOS process. To realize a low-loss and
high-Q implementation for on- chip CSRR, the CSRR can be etched directly
on a metal layer using signal lines as shown in Figure 2.14. Compared with
the prev ious method [7 8], CSRRs on a metal layer can form much stronge r
coupling between T-line and CSRR be cause they are on the same metal layer.
Resonator 219
Figure 9 .5: Simulated Γ and quality factor (Q) of SRR/T-line unit
cell at resonance.
More EM-energy can thereby be stored in the resonator and in turn results
in a higher Q-factor.
In this work, a differential CSRR structure is proposed in Figur e 9.6 to
provide a compact area. Both inputs are desig ne d on the sa me side to pro-
vide an AC ground for easy DC supply, which further reduces the potential
Figure 9 .6: On-chip differential T-line loaded with CSRR.
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