10 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
by the loss of meta l and substrate and antenna size, respectively. In o rder to
overcome the above difficulties and des ign a high-performance THz imaging
system in CMOS process, the design of a high-Q passive structure is required
in every part of the ima ging system to replace the conversional tr ansmission
lines (T-line) or LC-tank resonators, which usually suffer fro m larg e size and
low quality facto r in THz and greatly limit the system pe rformance.
1.3.2 THz CMOS Communication
The ever-expanding data size in various applications and associated increasing
processing capability and memory size in mobile devices call fo r high-data -rate
communication systems which can handle multi-Gbps data rate with compac t
size and low p ower consumption at the order of hundreds of mW or less. For
example, the 5∼9GHz license-free band at 60 GHz is attractive to meet these
requirements.
For short distance communication with lower power consumption, nor-
mally line- of-sight set-up is used due to the high attenuation from passing
through (around 40∼5 0 dB) and reflection from (around 10∼20 dB) a wall.
As a result, the distance is normally targeted around ten meters or below to
cover the distance within a room.
Recently, there has been extens ive research on short distance THz com-
munication systems [36, 37, 38, 39, 40, 41, 42, 43, 44, 45]. The potential
applications are the wireless High Definition Media Interface (HDMI) where
you can have an uncompress ed high-definition movie transferred from laptop
and displayed on TV in real time; and Personal Area Network (PAN), wher e
a wire less link could be used to replace various cables used in home, and
connect all e lectronic devices together with high-data-rate router s to provide
smart house applications.
Compared with I II-V technologies, CMOS shows various advantages.
Firstly, a high integration c an be provided due to the lower power c onsump-
tion of digital signal processing in C MOS. A high integration also lowers cost
from multi-die package and improves performance with elimination of high-
frequency IOs. Secondly, a low cost can be obtained. In addition to the lower
fabrication cost compared with III-V technologies and lower package cost, the
testing cost c an also be lar gely reduced with built-in-self-test (BIST) inte-
grated on chip.
However, CMOS also brings various design challenges. For example, scaled
CMOS transistors with lower supply voltage in advanced technologies can
largely r educe size and dynamic power for digital processing. Unfortunately,
many Figure-of-Merits (FOMs) in the frontend such as output power, linear-
ity, and nois e all degrades along with reduced supply voltage. Furthermore,
large Process-Voltage-Temperature (PVT) variation tends to occur with ad-
vanced CMOS technologies, which makes RF design less accurate and poses
requirement on extra bandwidth to cover. These design challenges motivate