140 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
6.3 Circuit Prototyping and Simulation
The designed 60-GHz PLO prototype is implemented in Global Foundries
65nm CMOS 1P8M technology as shown in Fig. 6.6 with a die size of 700µm ×
680µm excluding pa ds. B oth the 60-GHz VCO and 60-GHz divider chain have
been fabricated separately with measurement results. The VCO measurement
was shown in Section 4.4.3.
6.3.1 Divider Measurement Results
Figure 6.7 shows the chip micro-photo of the fabricated divider, which occupies
a core area of 0.058 mm
2
. The DC power of the ILFD is 6.3 mW under 0.75-
V power supply. The whole divider circuit is designed and verified with EM
simulation (ADS-Momentum) b efore fabrication. The measurements are then
done on a CASCADE Microtech Elite-300 probe sta tion with Agilent PNA-X
sp ectrum analyzer.
Figure 6.8 shows the mea sured input sensitivity curve. Two sub-bands are
clearly observed by switching inductor loaded transformer. T he first sub-band
has a free-running frequenc y around 63 GHz, and the sec ond sub-band has a
free-running frequency around 66 GHz. The input power is 0 dBm, and the
locking range for the first band is from 60.8 to 65.1 GHz, while the locking
Figure 6.6: Chip m icrography of 60-GHz PLL in Global Foundries 65
nm technology.
Phase-Locked Loop 141
Figure 6 .7: 60-GHz divider chain die photo.
Figure 6 .8: Measured sensitivity curve of the 60-GHz ILFD.
range for the s econd band is from 64.7 to 67GHz. The obtained total locking
range is thus 9.7% from 60.8 to 67 GHz, with a center fr equency of 63.9
GHz. Figure 6.9(a) s hows the ILFD output spectrum at 63 GHz after the first
division, where a 31.5-GHz signal is obtained. The functionality of the full
divider chain is also examined. Figure 6.9(b) shows the divide-by-8 divider
chain output spectrum at 6 3 GHz, where a 7.875-GHz output is obtained.
142 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
(a) (b)
Figure 6.9: Measured divide-by-2 and divide-by-8 output spectrums
at 63-GHz input signal.
6.3.2 PLL Simulation Results
The designed PLL is simulated in C adence. Figure 6.10 shows the transient
simulation of the locking process at the 3rd band (62.64 GHz). The control
voltage is settled to 783 mV at around 7 µs.
Figure 6.10: Simulated lockin g process of designed 60-GHz PLL at
62.64 GHz.
Phase-Locked Loop 143
Table 6.1: Simulated DC Power Comparison
Building blocks
Current
(mA)
Supply
(V)
Power
(mW)
Charge Pump
2 1.2 2.4
PFD
Programmable Divider
1.85 1.2 2.22
Shaping Buffer
DCML /4 divider
3 1.2 3.6
30 GHz divider
5.5 1.2 6.6
60 GHz divider
9 0.8 7.2
LO buffer
15 1.2 18
Oscillator
22 1.2 26.4
Total
66.4
Table 6.2: Performance Summary and Comparison with State-of-the-
Art CMOS 60-GHz PLLs
[188] [189] [190] [191]
This
work
(sim.)
Technology (CMOS)
90nm 90nm 90nm 65nm 65nm
VCO tuning range
(GHz)
61.1-
63.1
58-60.4
78.1-
78.8
75.6-
76.3
57-65.5
Phase noise (dBc/Hz
@1MHz)
-80 -85.1 -85 -85.3
-95
-89
Supply (V)
1.2 1.2 1.2 1.2 1.2
Reference freq. (MHz)
60 234.1 75 700 27
Power (mW)
78 80 101 73 66.4
Core area (mm
2
)
0.36 0.95 0.62
N.A.
0.41 (w/o
LPF)
Table 6.1 summarizes the DC power consumption in each block of the
PLL. The total power consumption is 66.4 mW including buffers.
The PLL performanc e is summarized in Table 6.2 with comparison to
state-of-the-art CMOS 60-GHz PLLs. Our work can provide a wide tuning
range (57 –65.5 GHz) with good phase noise performance (-95 dBc/Hz @1
MHz).
..................Content has been hidden....................
You can't read the all page of ebook, please click here login for view all page.