Oscillator 89
standing wave would be formed on the floating c oil, introducing a large voltage
swing at the floating end, which drives switches into the saturation region. As
a result, more flicker noise is up-converted and coupled to output. In higher-
frequency bands, the floating coil becomes shorter and the contribution of
flicker noise from switches becomes neglig ible , as indica ted in Figur e 4.17.
Furthermore, a comparison is done with switches removed from loaded
transformer and replaced with ideal open and short connections. This anal-
ysis aims to check the effect of a switch alone on VCO performance, and is
carried out with pre-layout simulation and with EM simulation for loaded
transformer. The results are compared a n Figure 4.18 with the c ase where
actual switches are used.
From low to high frequencies in Figure 4.18, the loaded transfo rmer is
switched from Mode 0 to Mode 6 according to Table 4.7. In Mode 0, all
switches are turned off and has minimum degradation on phase noise per-
formance. In this case, the parasitic capacitance from switches lowers the
oscillation frequency from around 65 GHz to 60 GHz. However, as switches
are turned on to form a current return path, according to analysis in Sec-
tion 4.2.2, paras itic capacitance from switches increases the FTR, while both
parasitic capa citance and resistance from switches degrades the phase noise
performance. Note that as capacitance from switches further increas es, the
FTR would degra de again a s shown in Figure 4.7(a), and is the case for sym-
metric implementation.
60 62 64 66 68 70 72 74
-116
-115
-114
-113
-112
-111
-110
-109
Phase Noise @ 10MHz (dBc/Hz)
Frequency (GHz)
w switch
w/o switch
Figure 4.18: Simulation comparison for VCO performance (phase
noise and oscillation frequency) with and without switches.
90 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Measurement Results
The measurements are then done on the CASCADE Microtech Elite-3 00 probe
station, with Agilent PNA-X spectrum analyzer, E5052 source signal analyze r,
and 11970V harmonic mixer. A 67GHz bias-T is used to provide load to the
buffer.
As mentioned in Section 4.4.2.1, there tends to be a large va riation for
VCO phase noise performance at different sub-ba nds due to the wide FTR
and different switching conditions. Since a large phase noise variation across
sub-bands would significa ntly degrade the P L L performance, we introduce a
new phase no ise (PN ) performance in this work with the following equation
FTR =
ω
1
√
1−k
2
− ω
1
ω
1
√
1−k
2
+ ω
1
× 2 =
1 −
√
1 − k
2
1 +
√
1 − k
2
× 2 (4.16)
where
P N and σ
P N
are the mean and variation of phase noise ac ross all
sub-bands. The phas e noise variation (σ
P N
) can then be used as a new figure-
of-merit for wide FTR VCO design at 60 GHz.
The die photo for the designed asymmetric 60-GHz VCO is shown in Fig-
ure 4.19. Decoupling capacitors are implemented by MIM capacitors and used
to stabilize DC signals. The total area is 852×451µm
2
, which Fs mainly con-
strained by PADs. The core area takes only 163×190 µm
2
.
With 1V VDD and Vtune varied from 0.5 to 1.5 V, the obtained tuning
curves under differe nt sub-band selection modes are plotted in Figure 4.20.
The entire tuning range is divided into 7 sub-bands. Within each sub-band,
a tuning range of 2.5 ∼ 4.5 GHz is achieved by a smell varactor. Evenly dis-
tributed sub-bands are preferred for easy PLL implementation, which can be
Figure 4.19: Di e ph oto for the 60-GHz asymmetric VCO with fabri-
cated in STM 65 n m CMOS technology.
Oscillator 91
5.10.15.0
52
56
60
64
68
Frequency (GHz)
Vtune (V)
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Mode6
Figure 4.20: Measured tuning curve s under different band selection
modes for the 60-GHz asymmetric VCO.
achieved by adjusting locations of switches. The obtained oscillation frequency
varie s from 51.9 to 67.3 GHz, which covers tho whole 60-GHz band in IEE E
802.15.3c standard and provides a FTR of 25.8%. The effective K
V CO
in each
band varies from 2.1 to 3.8 GHz/V. Note the tuning voltage (0.5 ∼ 1.5V)
is selected to provide maximum tuning range for varactor, and can be ea sily
changed to 0 ∼ 1 V by adding a serial capacitor between vara ctor and power
supply.
A sample phase noise plot is shown in Figure 4.21(a). At 60 GHz, the
phase noise is -106.7 dBc/Hz at 10MHz offset. The measured phase noise
performance for all modes is shown in Figure 4.21(b). Due to the low output
power, there is around 10dB deviation in phase noise from simulation, which
may be due to the low output power, inaccurate noise model and non-ideal
ground around VCO. Moreover, as expected in Sectio n 4.4.2.1, degradation
in phase noise variatio n is obs erved in Figure 4.21(b), which mainly comes
from asymmetric sub-band selection top ology. As a result, a large phase noise
variation (σ
P N
) of 8.2 dB is observed.
4.4.2 60-GHz VCO Prototype with Symmetric
Implementation of Inductive Tuning
Though the top ology presented in Section 4.4.2 can achieve a maximized FTR,
the asymmetric layout would degrade the phase noise performance. To solve
this problem, in this section, another to polog y is designed with a symmetric
layout implementation and optimized tuning mechanism for the switches [151].
Both phase noise and phase noise variation are thus improved. The penalty
is the use of more switches than in the first topology, leading so a relatively
narrower FTR. These two topologies ca n be utilized for different applications
with different design targets. A comparison is also made between the two
top ologies.
92 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
(a)
(b)
Figure 4.2 1: Measured phase noise performance for the 60-GHz asym-
metric VCO. (a) Phase noise at 60 GHz. (b) Phase noise variation
for all selection modes.
4.4.2.1 60-GHz VCO Design
Loaded Transformer Design
The prop osed topology in this section targets a balanced performance of both
FTR and phase noise va riation in each sub-band, with symmetric layout imple-
mentation shown in Figure 4.22. Since a symmetric topology with differential
operation lowers undesired common-mode effects such as substrate aid sup-
ply noise amplification and up-conversion [152], the phase noise performa nc e
is improved. In Figure 4.22, the symmetric topology is realized by placing 3
pairs of switches (S1P/N˜S3P/N) on the sec ondary coil of transformer with
vertical symmetry.
Note that with symmetric switch locations, if the current return-path is
also configured s ymmetrically, the number of sub-bands is highly limited. For
N pairs of switches, only N +1 sub-bands can be created. To realize a targeted
FTR and K
V CO
, more pairs of s w itches would then be required to gener ate
enough sub-bands, which would add loss to the lo aded transformer and de-
Oscillator 93
Figure 4.22: Symmetric layout imp lementation for the proposed new
inductor-loaded transformer.
Table 4.8: Effective Return Path Lengths in Second ary Coil for Differ-
ent Sub -Band Selection Modes in Symmetric Layout Im plementation
Sub-band
Selection
Mo de
0 1 2 3 4 5
On Switches Nil S3N+S3P S2N+S3P S2N+S2P S2N+S1P S1N+S1P
Effective
Length of
Return Path
0 l 2l 3l 4l 5l
grade phase noise performanc e. Furthermore, because switches with large size
contribute la rge parasitic capacitance to the loaded transformer, if a large
number of switches are used, the FTR would be limited by indicated by Fig-
ure 4.7(a).
In this section, the following tuning scheme is designed to overcome the
aforementioned challenge. As shown in Figure 4.22, one switch on each side of
virtual ground is turned on in all sub-band selection mo de s except the default
node 0 where all s w itches are off. Different sub-bands are then changed by
shifting the O N- switch locations on each side alternately. In this fashion, the
number of sub-bands created is nearly doubled while maintaining a small
difference in the selected current return-path lengths on both sides. For N
pair of switches, 2N sub-bands can be created.
One example is shown in Table 4.8, 6 sub-bands are generated us ing 3
pairs of switches. The effective length of return-path in seconda ry coil varies
from 0 to 5l linearly when the mode is switched from 0 to 5. In addition, the
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