36 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
quality factor of the co upling T-line, respectively. Ideally, with N oscillator
unit-cells co upled, the phase noise is N times smaller compared to the single
free-running o scillator. Note that similar improvement cannot be achieved by
sp ending the same amount power at one single oscillator. Firstly, increasing
the supply voltage close to the breakdown voltage has serious reliability issues;
secondly, phase nois e cannot be reduced when increasing the supply voltage.
2.4.2 Coherent Transmission
A single-ended dual-fed distributed amplifier (SEDFDA) topology can be used
to realize distributed amplification with extra bandwidth traded for better
power performance. CRLH T-line-based ZP S is implemented in SEDFDA to
optimize all transistors’ power performanc e simultaneously with compact size
and low loss.
A 2D active CRLH T-line network is further proposed as the power-
combining topology with high power-combining efficienc y. The ZPS connec-
tions in the pro posed 2D a ctive CRLH T-line network are adjusted such that
each combining branch resembles a SEDFDA with ZPS connection. In this
way, both high-e fficient power combining and distributed a mplification can be
simultaneously achieved.
Figure 2.17 shows the singe-ended version o f the proposed power-
combining topology. B y using C RLH T-line realized Z PS, a new 2D distributed
power-combining network can be constructed. The CRLH unit-cell can replace
the traditional λ/2 T-line foe in-phase distributed amplification along hori-
zontal direction to achieve the serial power combining. The parallel power
combining for all horizontal branches is then realized by zero-degree power
combiner with sho rt equal-length T-lines along the vertical direction. With
the serial power combining in the 1st level and parallel power combining in
the 2
nd
level, a 2D distributer power combining network is realized for simul-
taneous distributed amplification and power-combining. Such a topology can
be further extended for pha sed-array applications by replacing ZPS with an
array of tunable phase-shifters.
The proposed topology can simultaneously improve power and bandwidth
performance o f PA. For example, PA power performance can bo viewed from
two aspects: output power per area (P
out
/area ) and output power per DC
power consumption (PAE). The 2D power-combining network provides a high
density of transistor, and therefore improves P
out
/area . T he distributed topol-
ogy provides a wide bandwidth, while the SEDFDA implemented with CRLH
T-line-based ZPS trades extra bandwidth with improved efficiency, thus im-
proving PAE. As a result, the power performance can be improved together
with bandwidth performance.
Note that for a fix ed transistor size, the total o utput power depends on the
number of distributed stages N and parallel combining branches M. Therefore,
the power handling ability of the proposed PA partially depends on distr ibuted
stage numbe r N, which is limited by the T-line loss and phase error.