Power Combiner 193
(a)
(b)
Figure 7.43: DAC control of PA output power and improved effi-
ciency during power back-off. (a) Comparison of drain efficiency dur-
ing power back-off for PA with and without DAC control to obtain
the sage output power at 58.3GHz. (b) Summarized efficiency im-
provement for different ou tput power level (DAC modes) at different
frequencies.
efficiency curve is plotted by vary ing the input power to the PA with the
DAC turned o ff to achieve the same o utput power level. As shown in Fig ure
7.43(a), though the PA with DAC control also shows degradation in efficiency
during power back-off due to deviation of biasing from optimum point, the
efficiency is still largely improved compared with PA witho ut digital control.
For example, an improvement of 175% (by dividing the two dra in efficiency
values) is achieved for PA efficiency at Mode 1. The improvement in drain
efficiency at different freque nc ies for different DAC modes and thus different
194 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
0.00 0.05 0.10 0.15 0.20 0.25 0.30
0
1
2
3
4
5
6
7
ADC Out
Pout (mW)
Figure 7.44: ADC outputs for PA output power detection at 58.3
GHz.
Figure 7 .45: Modification for the power detector design.
back-off levels is further summarized in Figure 7.43(b). An improvement from
170% to 190% is obtained at Mode 1 for the whole 60GHz band.
The power detection for the PA’s output power is further measured with
the results shown in Figure 7.44. Since a square root detector is used which
has output voltage proportional to the squar e of the signal’s voltage swing ,
mm is used for the X-axis. Figure 7.44 shows the measurement results at
center frequency (58.3GHz). The 3-bit ADC outputs 8 digital le vels as the
PA’s output power varies from 0 to 0.3 mW.
Note the detectable power range deviates from the originally designed
power ra nge near OP
1dB
level. This can be explained by the designed tower
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