240 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 10.7: EM-simulation-based comparison of DTL-CSRR and LC-
tank resonator for CMOS 96 GHz SRX de sign.
and individual finger width of transistors in Figure 10.8, r espectively. And the
channel length of every active de vice is 60nm. The remaining circuit consists
of a common source input buffer (M1) for current injection and an envelope
detector formed by M5 and M6. The common source sta ge (M1) is designed
for input signal injection and a lso reverse isolation from the oscillator to the
input. The size o f M1 is optimized with consideration of minimized parasitic
capacitance as well as the input matching. Similarly, M5 and M6 als o need to
be minimized but doing so will reduce the detection efficiency. To solve this
problem, a capacitance coupling by C1 and C2 is introduced between the out-
puts of the o scillator tank and the e nvelope detection. Firstly, the capacitance
loading from M5 and M6 is reduced by series c onnection of the coupling capac-
itors; se condly, M5 and M6 are biased externally by large resistors (R1, R2)
to optimize the detection; thirdly, 1/f noise fro m M5 and M6 is also isola ted.
10.3.3 SRX Design by TL-SRR
10.3.3.1 Diff e rential T-Line Loaded with SRR
The TL-SRR structur e with horizontal placement of SRRs (Figure 2.13) is also
not suitable for the practical implementation for SRX, mainly due to the larg e
area overhead. Compared to TL-CSRR, TL-SRR inherently has better layout
flexibility because SRRs can be vertically stacke d within a compact area. One
differential T-line loaded with stacked SRRs (DTL-SRR) is proposed in this
work for the application of 135 GHz SRX design in the 65nm CMOS RF
process.
As shown in Figure 10.9(a), the DTL- SRR is designed by stacked SRRs
with the same dimensions of 24 × 24 µm
2
in 4 metal layers (M5 to M8). All