220 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
coupling to the lossy substrate. Note that the metamaterial property of the
proposed differential T-line-loaded CSRR and its high-Q feature can be illus-
trated through simulation as follows.
For example, the metamaterial pro perty can be calculated from S-
parameters by [242, 243]
cos(nkd) =
1 − S
2
11
+ S
2
21
2S
21
,
z = ±
s
(1 + S
11
)
2
− S
2
21
(1 − S
11
)
2
− S
2
21
,
ε =
n
z
, µ = nz, (9.3)
where n is the refractive index, z is the wave-impedance, k is wave-factor, and
d is the physical length. Because the metamaterial is considered as a passive
medium, the signs of n a nd z in (9.3) can be determined by two requirements:
ℑ(n) ≥ 0 and ℜ(z) ≥ 0, where ℑ(n) and ℜ(z) denote the imaginar y part and
real part of n and z, respectively.
Based on (9.3), one can characterize the metamater ial res onator as follows.
The proposed DTL-CSRR str uc ture in Figure 9.6 is implemented on chip
with resonance frequency biased around 100 GHz. ADS Momentum is used
for the EM s imulation to obtain the S-parameters. As shown in Figure 9.7, a
negative µ can be observed within a narrow band near the resonance frequency.
As stated earlier, the negative µ and positive ε create the electric plasma,
where the propagating EM-waves beco me evanescent waves and are largely
reflected backward. The deep rejection fre quency band with a sharp cut-off
can be viewed from S12 plot in Figure 9.7, which corresponds to a high-Q
performance.
The Q-factor can be estimated from the simulation by Q = f
0
/BW
−3dB
,
where f
0
is the resonance frequency and BW
3dB
is the bandwidth. As such,
the obtained Q-factor is 65, which is much higher than the normal Q value by
a resonator composed of L C -tank at similar frequency, around 30 as indicated
in [244].
9.4 Circuit Prototyping and Measurement
9.4.1 76-GHz D ifferential TL-SRR Resonator
Firstly, as shown in Figure 9.8, the DTL-SRR-based metamaterial oscillator
has the property of position-dependent voltage-c urrent amplitudes. If a cro ss-
coupled transistor pair is connected to the opened ends of the two striplines
in the host T-lines, an os cillation can be sustained at the specified frequency
according to the length o f the str iplines. The incident-wave energy is injected
by the cross-coupled inverters propagates in forward waves along the T-line
Resonator 221
Figure 9.7: EM characterization of the proposed differential CSRR
resonator.
Figure 9 .8: Voltage distribution of the DTL-SRR-based resonator.
toward the short point; the energy is reflected at SRR load; and the reverse-
wave has a superposition of the incident-wave and leads to a resonance if in
phase. Stronger wave reflection means less loss and higher Q of the reso nator
for oscillation.
222 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 9 .9: Schematic of the DTL-SRR-based oscillator.
As a result, with the use of the proposed metamaterial resonator by DTL-
SRR, a 76GHz oscillator is designed. As shown in Figure 9.9, a pa ir of cr oss-
coupled NMOS transistors is deployed as the negative resistor to compensate
the energy loss in the resonato r. Sour ce-follower output buffers are imple-
mented with off-chip bias T to save are a. The supply-voltage for the resonator
is provided from the middle point of the T-line short-circ uit termination, which
is a differential zero AC-voltage point. External current source is fed into the
chip through a DC-PAD and mirrored to the core circuit of oscilla tor to con-
trol the power consumption. In addition, for comparison, the standing-wave
resonator by coplanar stripline (CPS) under the same resonant frequency is
also implemented in the same chip with geo metries shown in Figure 9.2(b).
For a fair comparison, the proposed two oscillators have the same size and
layout designs of cross-coupled NMOS trans istors and output buffers, except
for resonators. The channel length of transistor is chosen to the minimum 60
nm allowed by the technology to reduce the parasitic effects, while the width
Resonator 223
is 6 µm (each finger width is 1 µm) for both the cross-c oupled pair and the
source-follower output buffers. The detailed physical sizes in Figure 9.2 show
that the use of SRR has 40% area reductio n versus the use of CPS.
9.4.2 96-GHz D ifferential TL-CSRR Resonator
Next, a 96GHz oscillator is also implemented in the same CMOS 65nm process
with the use of metamaterial resonator by DTL-CSRR. Similarly, the loss from
the resonator is compensated by a c ross-coupled pair of NMOS transistor s,
as shown in Figure 9.10. To obtain the maximum f
MAX
of NMOS transis-
tors, the indiv idual fing er width is designed to be 1 µm [245], and the total
finger number is designed to be 8 to sustain the oscillation on slow-corner
while minimizing parasitic capacita nc e. In orde r to isolate the oscillato r from
the peripheral circuits and also to provide enough output power, the out-
put is designed together with on- chip buffer and RF choke. It is composed
of a quarter-wavelength slow-wave T-line and de-coupling capac itor. All four
transistors in the circuit are self-biased. The DC-supply voltages for the core
oscillator and buffer-stage are provided sepa rately to identify the individual
current consumption. Note that the 1 -metal-layer design of resonator used for
demonstration in Figure 2.14 is modified to be a 2-metal-layer design for os -
cillator implementation. Other than the benefit of size reduction, the stacked
structure is also expected to improve the Q-factor . Because the stacked two
CSRRs are in the opposite direction, they are excited in the odd mode at
resonance by the E-field in between, which avoids the E-field to penetrate
through the substrate. As such, the impact of the lossy substrate to the res-
onator Q-factor can be further reduced.
9.4.3 Measurements
The proposed 76-GHz SRR and 96-GHz CSRR oscillators were both is im-
plemented in the STM 65-nm CMOS RF process with f
T
/f
MAX
of 170/230
GHz. As shown in Figure 9.11, the RF and DC signals are connected thro ugh a
CASCADE Microtech Elite-300 probe station. The single-ended output of the
chip is connected to a phase-noise analyzer FSU-P50 from Rohde & Schwarz
(R&S) for the phase noise measurement at millimeter-wave frequency region.
To measure the signal frequency in 75 ∼ 110 GHz, a W-band harmonic mixer
FS-WR10 is used for down-conversion. The external Bias-T is req uired in the
measurement for DTL-SRR and SWO-based oscillator s at 76 GHz.
9.4.3.1 Results of 76G H z Oscillator with DTL-SRR
As shown by the die photo in Figure 9.12, both the DTL-SRR-based oscillator
and the standing-wave-oscillator (SWO) by coplanar stripline are implemented
side by side on the same chip with the same resonant frequency. The sizes
excluding RF-PADs is 310 × 210 µm
2
(0.06 mm
2
) for DTL-SRR, and 310 ×
224 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 9.10: Circuit diagram o f the 96 GHz CMOS oscillator with
the use of the proposed metamaterial resonator by CSRR structure.
270 µm
2
(0.08 mm
2
) for SWO. The proposed DTL-SRR oscillator consumes
only 2.7 mW from a 1-V power supply, which is slightly higher than the
power consumption of SWO of 2.63 mW from the s ame 1-V power supply.
The measured oscillation frequency of the DTL-SRR and SWO oscillators are
both observed at 76.1 GHz as shown in the spectrum diagram in Figures 9.13
and 9.14, where one spur contributed by the harmonic mixer can be observed
at 200 MHz away from the oscillation frequency. Here a signal identification
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