Coupled Oscillator Network 129
Figure 5.27: Schematic of injection-locked 70 GHz CON with 2 MPW
unit-cells.
proposed power splitter is shown in Figure 5.28 (a). The inlet single-ended 140-
GHz signal (P1) is first split into two path “a” at point; each of the resulting
single-ended 140GHz signals is further converted into differential signal by a
compact transformer-based balun (25×25µm
2
) due to the limited inter-stage
chip ar ea. The primary and secondary loops of the transformer-based baluns
are designed in the topmost (M8) and second topmost (M7) copper layers,
respectively. The grounding layer (M1) is removed under the balun to enhance
the inductive coupling between the primary and secondary loops. The phase
and magnitude mismatch between P2 and P3 (P4 and P5) can be improved
by adjusting the trace length and AC-GND locations o f the s econdary coils,
respectively. A symmetric layout of the whole splitter ensure the magnitude
and phase balance among differential port (P2-P3 and P4-P5) with S21 = S41
and S41 = S51. As verified by EM simulation in Figure 5.3.3.3, the proposed
the proposed power splitter has an average intrinsic loss of 9 dB at 140 GHz.
The magnitude a nd phase mismatches at 140 GHz are only 0.7 dB and 5.8
degrees, respectively.
5.3.3.4 17.5-GHz to 70-GHz Input Reference Frequency
Quadrupler
Figure 5.29 shows the schematic of the 17.5 GHz to 70 GHz input reference fre-
quency quadrupler . Based on the frequency doubler discussed in Sec. 5.3.2.1,
the proposed quadrupler is designed with additional push-push frequency dou-
bler from 17.5 GHz to 35 GHz. One transfor mer-based balun is deployed to
generate a differential 17.5 GHz reference signal to drive M1 and M2. Figure
5.30 shows the post-layout simulation results of the e ntire frequency quadru-
pler with 0-dBm reference power. The conversion gain is above -20 dB in 16
∼ 19 GHz. Due to the low coupling factor between the primary and the sec-
ondary coil in on-chip transformer-based balun at 17.5 GHz, the input S11
130 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 5.28: 140 GHz power splitter from one singl e-ended input
to two differential outputs. (a) On-chip layout, (b) EM-simulation
results.
is only smaller than -6 dB in 16 ∼ 17.3 GHz. This can be resolved by the
additional matching network in PCB.
5.3.3.5 Simulation Results and Discussion
The proposed injection-locked THz signal source is implemented in the 65nm
CMOS RF process with the Cadence layout shown in Figure 5.31. It ha s a
total a rea of 750 × 550 µm
2
, and a core area of 0.12 mm
2
including CONs at
70 GHz and 140 GHz. A post layout simulation is conducted to evaluate the
performance of the proposed 280-GHz signal source. Operating from a 1.2-V
power supply, the core of signal source consumes 288 mW, while the input
frequency quadrupler consumes another 7.6 mW.
Coupled Oscillator Network 131
Figure 5.29: Input reference frequency quadrupler from 17.5 GHz to
70 GHz.
Figure 5 .30: Post-layout simulation results of 17.5 GHz to 70 GHz
quadrupler.
Figure 5.32 shows the simulation results of output power. By adjusting
the reference signal around 17.5 GHz with 0-dBm power level, a 10.5% tuning
range centered at 286 GHz is obtained. The max imum output power of 1.9
mW is observed at 276 GHz with a DC-RF efficiency of 0.66%. Moreover, the
maximum power density o f the propos ed signal source is 31.1 mW/mm
2
. The
performance of the proposed 280 GHz signal source is summarized in Ta ble
5.3 with compariso n to the recent state-of-the-art THz signal sourc e designs
in CMOS process. It can be obser ved that the proposed 280 GHz signal source
has the highest power density as well as the outstanding output power and
132 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 5.31: Cadence layout of the proposed 280 GHz source in
CMOS.
Figure 5.32: Simulated output power of the proposed 280 GHz source
in CMOS.
..................Content has been hidden....................
You can't read the all page of ebook, please click here login for view all page.