Power Combiner 165
Figure 7 .13: RC networks for PA stabilization.
output power with the requirement of a higher supply voltage such as 2V
[192, 196, 208, 20 9, 210].
RC Network
The most conventional technique for PA sta biliz ation is to use an RC network
[211, 195]. As shown in Figure 7.13, with serial or parallel RC networks, high-
and low-frequency regions can be stabilized, respectively. More specifically, a
parallel RC ne twork put in serial connection forms a high pass topology, with
larger serial resistance introduced at lower frequency region, thus stabilizing
the new frequency. Similarly, a serial RC network put in parallel connection
forms a low pass topology, with smaller parallel resistance introduced at higher
frequency region, thus stabilizing the high frequency. These stabilization tech-
niques ca n be used by itself or work together with other techniques. Its penalty
is o bvious. To achieve a targeted stabilization level, additiona l losses are often
introduced in the operating region, degrading PA’s power gain and efficiency.
Technique Selection
Three stabilization techniques are summa rized above. There are other stabi-
lization techniques. For example, by properly designing the ma tching network,
the PA can be stabilization without using additional devices [194, 212]. How-
ever, as the ma tching needs to take stabilization into design consider ation, the
performance o f PA may not be fully o ptimized.
Based on the above analysis, the neutralization technique shows the best
performance without additional requirements and is selected in this work.
Although other techniques such as cas code topology and RC network may be
less sensitive to process variation, additional performance penalties or system
requirements can be caused.
In addition to the above intro duced stabilization techniques, automatic
digital control c ould also be used to mitig ate PVT-va riations [10, 213]. In
166 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
the following section, a power detecto r is implemented to quantify the output
power level with a DC signal. This DC s ignal could then be used for possible
self-healing or automatic digital control of PA.
7.3.4 Digital Control
As mentioned above, automatic digital control could also be used to mitig ate
PVT-variations [10, 213]. Hig h frequency in the mm-wave region and scaled
CMOS transistor siz e below 100nm make transistor performance susceptible
go process variation and make accurate modeling of both active a nd passive
elements very challenging. Furthermo re, power amplifier consumes large DC
power and normally gene rates a high temperature variation. All these varia -
tions would cause the power transistor to de viate from its optimal operating
point, which degrades performances much as output power, efficiency, linear-
ity, gain and stability. Furthermore, the operating environment is also likely to
vary, such as the variation of antenna load impedance. Aging is another con-
cern, where transistor performance would gradually change with time. Auto-
matic digital control provides solutions to all the above is sues. With a feedback
loop designed for self-healing, the PA bia sing and matching can be automati-
cally tuned for optimal pe rformance.
Except to maintain optimum PA performa nc e, another important func-
tion w hich can be provided by automatic digital control is to prevent circuit
destruction [88]. The low breakdown voltage provided by scaled CMOS tech-
nologies makes transistors vulnerable to environment change. For example, a
mismatch in antenna lo ad impedance may cause a p eak voltage higher than the
breakdown voltage. With automatic digital control, biasing point of transistor
can be monitored and controlled in the safe region, and emerge nc y shutdown
can also be provided. Furthermore, external testing contributes a large por-
tion of expense for circuit production. With the help o f o n-chip feedback and
digital control, a built-in self-test (BIST) mechanism can be provided which
is much cheaper [10]. In addition, digital control is explored and implemented
for the power back-off.
7.3.4.1 Power Back-Off in PA
Power back-off is often required for PA to conserve battery power, avoid inter-
ference with adjacent channels, and fulfill linearity requirement for adopted
modulation scheme [2 14, 215, 216]. The power back-off is usually realized
from baseband side by reducing input power to PA. Note that the high out-
put power e fficiency region for PA normally locates nea r P
1dB
and P
sat
points.
When input power is reduced, the PA operating point is pulled away from the
high-efficiency region, le ading to a large power waste, which is even worse for
CMOS PA design at 60GHz. To maintain high output power efficiency, digital
control can be introduced in PA design with back-off realized by self-tuning,
Power Combiner 167
which reduces the PA output power along with DC power to maintain a high
efficiency.
There are many techniques to enhance PA output power efficiency
for back-off. A few were successfully implemented at 60GHz and beyond
[204, 214, 215, 216]. Architectures such as the Doherty amplifier, out-phasing,
and envelope elimination and restoration (BER) show boosted back-off ef-
ficiency at low-frequency regions, but have high design complexity or large
power consumption from digital data pre-processing [216]. Multi-mode oper-
ation by turning on and off a differe nt numbe r of PA units is another popular
technique at low frequency [217, 218, 219, 220, 221, 222, 223], but with two
critical design issues at high frequency: power leakage to the PA units that
are switched off, and mismatching due to the impedance variation of PA units
at different modes [214]. There are two recent works [204, 214] with succ essful
implementations of multi-mode operation at 60GHz. The work in [204] tunes
the matching by shorting part of the power combiner, but the obtained PAE
for low-power mode has a large degradation compared with high-power mode.
The work in [2 14] isola tes the PA units in power-off made by implementing a
bulky quas i-quarter-wavelength transmission line to prevent current leakage.
In this work, power back-off is realized by controlling the current biasing
of transisto rs without PA switched off during power tack-off. It thus avoids
the power leakage and impedance mismatch issues in [204, 205, 2 06, 207, 2 08,
209, 210, 10, 213, 11, 214]. As DC power consumption is re duced along with
output power, high output power efficiency can be maintained.
7.3.4.2 Power Detection
On chip power detection is widely used in mm-wave regions [10, 213, 11, 12,
13]. In addition to providing dynamic bias c ontrol to mitigate the e ffect of
process, voltage a nd temperature variations (PVT-variations) [10, 213], it can
also be use d to cope w ith antenna impedance mismatch [10, 11], realize low-
cost on-chip built-in self-test (BIST) [10, 12], and provide VSWR protection
with co nsideration for transistor breakdown and system overload by offering
protection mechanisms such as emergency shutdown [10].
As shown in Figure 7.14, a p ower detection unit is normally formed by
two parts: a power coupler which senses the output power le vel, and a power
detector which transfers the sensed sig nal’s power level to a DC signal. Dif-
ferent topologies are analyzed and designed in this section for power coupler
and p ower detector, respectively.
Power Coupler
Power coupler senses the output power by coupling a fraction of the output
signal. In mm-wave regions, two types of power couplers are found in literature.
The first type (Figure 7.15(a)), which is also the more common one, is to use
a c apacitive coupling from the tr ansmission line feeding to the output port
[10, 11, 12]. The capacitive coupling level is usually designed low so that the
168 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 7 .14: Power detection unit.
(a) (b)
Figure 7.15: Power coupler topologies: (a) capacitive coupling from
output [10, 11, 12]; (b) direct connection from output [13].
output le vel is merely affected. The coupled signal often goes underneath the
T-line (and its ground if it’s CPW topology) and suffers more loss from the
substrate. Considering the low coupling level, the sens itivity of power detection
is low. The second type of power coupler (Figure 7.15(b)) is proposed in [13],
with the p ower coupler merged into the DAT power combiner. The power
coupling is achieved through direct line connection. As a result, the output
power level would be affected, and the input impedance for power detector
must be considered as part of the output matching network. The benefit is the
easy connection to power detector and high sensitivity of the power detection
unit.
In this work, power detection is designed with the objective to c ontrol the
DC power a long with output power and improve PA efficie nc y during power
Power Combiner 169
Figure 7 .16: Desig ned capacitive power coupler.
back-off. Therefore, the degradation on output power level caused by powe r
detection needs to be minimized, while the sensitivity requirement on power
detection is not critical and can be relaxed. As a result, the first type of power
coupler is selec ted. The designed layout is shown in Figure 7.16. A metal-
plate capacitor is implemented a t the conjunction of a two-branch combiner.
The combiner is implemented at top metal level, and the coupled signal is fed
to the power de tec tor through the second top metal level. Since micro-strip
top ology is adopted for trans mis sion line design, the resulting power coupler
is very compact.
Power Detector
In the mm-wave region, square-law power detector is commonly used for on-
chip applications [10, 11], with the simplified schematic shown in Figure 7.17.
Coupled signals are fed into differential transistor pair Mn1 and Mn2, with
their output terminals connected together. With an input signal of V
IN
±
V
ac
cosωt, the combined current flowing through the two transistors (I
d
1+I
d
2)
can be approximated with a simple square-law equation for CMOS transistors:
I
d
1 + I
d
2 = K
n
2
V
eff
2
+ 2V
2
ac
cos
2
ωt
= K
n
2
V
eff
2
+ V
2
ac
cos2ωt + V
2
ac
(7.8)
where
V
eff
= V
IN
− V
th
is an offset which can be canceled through current
mirror. K
n
is the coefficient in square-law equation for NMOS transistors Mn1
and Mn2. The amplitude of the AC signal is represented by V
ac
.
When this current is mirrored through the low-pass filter, the high fr e-
quency term V
2
ac
cos2ωt is filtered out. As a result, the output current I
out
becomes proportional to V
2
ac
, which represents the power level of the AC sig-
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