xvi List of Figures
5.26 (a) Schematic of injection-locked 140 GHz CON with 4 MPW
unit-cells; (b) 2nd harmonic outputs power combining net-
work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.27 Schematic of injection-locked 70 GHz CON with 2 MPW unit-
cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.28 140 GHz power splitter from one single-ended input to two
differential outputs. . . . . . . . . . . . . . . . . . . . . . . . 130
5.29 Input reference frequency quadrupler from 17 .5 GHz to 70
GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.30 Post-layout simulation results of 17.5 GHz to 70 GHz quadru-
pler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.31 Cadence layout of the proposed 280 GHz source in CMO S. . 132
5.32 Simulated output power of the proposed 2 80 GHz source in
CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
6.1 Schematic of designed CMOS 6 0-GHz P L L . . . . . . . . . . 136
6.2 Layout o f designed CMOS 60-GHz PL L . . . . . . . . . . . . 136
6.3 Schematic of switch-inductor loaded transformer-based ILFD. 138
6.4 Schematic of the 30-GHz ILFD. . . . . . . . . . . . . . . . . 139
6.5 Schematic of the 60-GHz divider chain. . . . . . . . . . . . . 139
6.6 Chip micrography of 60-GHz PLL in Global Foundries 65 nm
technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.7 60-GHz divider chain die photo. . . . . . . . . . . . . . . . . 141
6.8 Measured sensitivity c urve of the 60-GHz ILFD. . . . . . . . 141
6.9 Measured divide-by-2 and divide-by-8 output spectrums at
63-GHz input signal. . . . . . . . . . . . . . . . . . . . . . . 142
6.10 Simulated locking process of designed 60-GHz PLL at 62.64
GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.1 Proposed 2D active CRLH T-line network. . . . . . . . . . . 14 9
7.2 Distributed amplifier (DA) topologies: (a) conventional DA,
(b) tapered DA, (c) DFDA, (d) SEDFDA. . . . . . . . . . . 151
7.3 Equivalent circ uit for single-ended dual-fed distributed ampli-
fier (SEDFDA). . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.4 Effect of T-line loss on SEDFDA performance. . . . . . . . . 154
7.5 Effect of T-line phase error on SEDFDA performance: (a) 3D
diagram, (b) contour diagram. . . . . . . . . . . . . . . . . . 156
7.6 Traditional right-handed T-line analysis. . . . . . . . . . . . 158
7.7 Zero-phase CRLH T-line analysis: lumped model and Smith
chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
7.8 Design consideration for the proposed 2D distributed power
combining network. . . . . . . . . . . . . . . . . . . . . . . . 159
7.9 Differential version of propos ed SEDFDA PA topology based
on 2D distributed power c ombining network with the use of
CRLH ZPSs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
List of Figures x vii
7.10 The proposed layout for differential 2D powe r combining net-
work. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
7.11 Neutralization technique for PA stabilization. . . . . . . . . 163
7.12 Cascode topology for PA stabilization. . . . . . . . . . . . . 164
7.13 RC networks for PA stabilization. . . . . . . . . . . . . . . . 165
7.14 Power detection unit. . . . . . . . . . . . . . . . . . . . . . . 168
7.15 Power coupler topologies: (a) capacitive coupling from output;
(b) direct connection from output. . . . . . . . . . . . . . . . 168
7.16 Designed capacitive power coupler. . . . . . . . . . . . . . . 169
7.17 Square-law power detector. . . . . . . . . . . . . . . . . . . . 170
7.18 Designed single- ended square low power detector. . . . . . . 171
7.19 Designed digital control system. . . . . . . . . . . . . . . . . 171
7.20 ADC design: (a) flash ADC topology; (b) resistor array to
generate reference voltage. . . . . . . . . . . . . . . . . . . . 172
7.21 Comparator top ologies for ADC des ign: (a) n-type; (b) p-type. 173
7.22 8-to-3 encoder for ADC design: (a) Q0, (b) Q1, (c) Q2. . . . 174
7.23 DAC topology. . . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.24 Schematic o f 2-stag e PA with a 2×2 distributed power com-
bining network. . . . . . . . . . . . . . . . . . . . . . . . . . 175
7.25 Simulated and meas ured S parameters of PA under 1.2 V sup-
ply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
7.26 Reverse isolation and stability of PA under 1.2 V supply. . . 177
7.27 Measured power and PAE of PA at 52 GHz under 1.2 V
supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
7.28 Die micrograph with block illustr ations. . . . . . . . . . . . 179
7.29 On-chip implementation of CRLH T-line (metamaterial) to
realize zero-phase shift in standard CMOS technology for the
60 GHz PA prototype with differential 2×4 distributed power
combining network. . . . . . . . . . . . . . . . . . . . . . . . 180
7.30 Schematic of 3-stage differential PA with differ ential 2 ×4 dis-
tributed power combining network. . . . . . . . . . . . . . . 181
7.31 Die micrograph of PA with 2D power combining network by
zero-phase-shifter. . . . . . . . . . . . . . . . . . . . . . . . . 182
7.32 The measur ed S parameters of PA and its sta bility factor with
center frequency (63 GHz) under 1 V supply. . . . . . . . . . 183
7.33 The measured output power and PAE of PA at center fre-
quency (63 GHz) under 1 V supply. . . . . . . . . . . . . . . 184
7.34 On-chip implementation of CRLH T-line (metamaterial) to
realize zero-phase shift in standard CMOS technology for the
60 GHz PA prototype with differential 4×4 distributed power
combining network. . . . . . . . . . . . . . . . . . . . . . . . 184
7.35 EM simulation results of both loaded CRLH T-line and loaded
λ/2 T-line for comparison. . . . . . . . . . . . . . . . . . . . 185
xviii List of Figures
7.36 Schematic of the 60-GHz PA prototype with 3 stages and
differential 4×4 distributed power combining network a t 3
rd
stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 86
7.37 Simulated voltage swings on both distributed stages in the
gate line and drain line of designed 2D distributed power com-
biner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
7.38 Die micrograph of the 60 GHz PA prototype with differential
4×4 distributed power combining network. . . . . . . . . . . 188
7.39 The measured S parameters of the PA prototype and its sta-
bility factor under 1.2 V supply. . . . . . . . . . . . . . . . 189
7.40 The measured output power and PAE of the PA prototyp e at
center frequency (58.3 GHz) under 1.2-V supply. . . . . . . . 190
7.41 Measured power performance of the PA prototype over 60-
GHz band (57 ∼ 64 GHz), whe re >1 5 dBm OP
1dB
and >16
dBm P
sat
are obs erved with peak values of 16.6 dBm and 1 7.2
dBm, respectively. . . . . . . . . . . . . . . . . . . . . . . . . 190
7.42 Power performance (OP
1dB
and OP
1dB
/Area) compariso n of
both differential PA prototypes with 2×4 and 4×4 power com-
bining networks with state-of-the-art 6 0-GHz CMOS PAs. . 191
7.43 DAC control of PA output power and improve d efficiency dur-
ing power ba ck-off. . . . . . . . . . . . . . . . . . . . . . . . 193
7.44 ADC outputs for PA output power detection at 58.3 GHz. . 194
7.45 Modification for the power detector design. . . . . . . . . . . 194
8.1 Operation diagram of leaky wave antenna: (a) β > 0, (b)
β = 0, and (c) β < 0. . . . . . . . . . . . . . . . . . . . . . . 199
8.2 Geometrical configuration of the proposed SIW antenna with
four corner slots. . . . . . . . . . . . . . . . . . . . . . . . . 200
8.3 Design of on-chip integrated circular-polarized SIW antenna
in CMOS 65 nm process. . . . . . . . . . . . . . . . . . . . . 202
8.4 Stacking of high-resistivity Si layer on top of the LWA. . . . 203
8.5 Structure of CRLH T-line-based 2D phase-arrayed array in
THz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
8.6 Radiation efficiency enhanc ement by stacking a high-
resistivity Si layer. . . . . . . . . . . . . . . . . . . . . . . . . 204
8.7 Gain radiation patterns for the proposed 1D LWA array at
three frequencie s: f = 250 GHz (β < 0, backward radiation),
f = 280 GHz (β = 0, broadside radiation), and f = 290 GHz
(β > 0, forward radiation). . . . . . . . . . . . . . . . . . . . 205
8.8 Gain radiation patterns for the prop osed 2D LWA array
at three frequencies: f = 260 GHz, f = 280 GHz and f =
310 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
8.9 HFSS simulation results of proposed SIW antenna directivity
at 270 GHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
List of Figures xix
8.10 HFSS simulation results of the proposed SIW antenna radia-
tion pattern at 270 GHz. . . . . . . . . . . . . . . . . . . . . 207
8.11 HFSS simulation results of polarized vector electric field in the
slots of SIW cavity a t 270 GHz. . . . . . . . . . . . . . . . . 208
8.12 HFSS simulation r esults of input S11 and antenna axial ratio
on broadside radiation direction. . . . . . . . . . . . . . . . . 208
9.1 (a) Stacked SRR unit-cell designed by metal layers of M7 and
M6; (b) S21 simulation results with different stacking meth-
ods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
9.2 Geometries of resonators with slow-wave shielding. . . . . . 215
9.3 T-line-based SRR excitation. . . . . . . . . . . . . . . . . . . 216
9.4 Simulated Γ plot in Smith chart of SRR/T-line unit cell at
resonance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8
9.5 Simulated Γ and quality factor (Q) of SRR/T -line unit cell at
resonance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9
9.6 On-chip differential T-line loaded with CSRR. . . . . . . . . 219
9.7 EM characterization of the proposed differential CSRR res-
onator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
9.8 Voltage distribution of the DTL-SRR-based r esonator. . . . 221
9.9 Schematic of the DTL-SRR-based oscillator. . . . . . . . . . 222
9.10 Circuit diagram of the 96 GHz CMOS oscillator with the use
of the proposed metamaterial resonator by CSRR s tructure. 224
9.11 Equipment setup for W-band 75∼110 GHz phase noise mea-
surement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
9.12 Chip photo of the DTL-SRR-based osc illator and SWO. . . 225
9.13 Spectrum of the 76 GHz DTL-SRR oscillator. . . . . . . . . 226
9.14 Spectrum of the 76 GHz SWO. . . . . . . . . . . . . . . . . 227
9.15 Phase noise mea surement and simulation results of the 76 GHz
DTL-SRR oscillator and SWO. . . . . . . . . . . . . . . . . 227
9.16 Chip photo of the DTL-CSRR-based oscillator. . . . . . . . 2 28
9.17 Spectrum of the 96-GHz oscillator with DTL-CSRR. . . . . 229
9.18 Phase noise measurement and simulation results of 96 GHz
oscillator with DTL-CSRR. . . . . . . . . . . . . . . . . . . 229
10.1 CMOS THz imager array. . . . . . . . . . . . . . . . . . . . 232
10.2 (a) Block diagram of super-regenerative receiver; (b) impact
of resonator Q-factor to receiver sensitivity. . . . . . . . . . . 232
10.3 Simplified equivalent circuit model of sup er-regenerative am-
plifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
10.4 Reflection coefficient of T-line loaded with CSRR unit-cells. 237
10.5 Reflection loss compensation by cross -coupled NMOS pair
with controlled tail current. . . . . . . . . . . . . . . . . . . 238
10.6 Layout for CMOS o n-chip implementation of DTL-CSRR for
96 GHz SRX. . . . . . . . . . . . . . . . . . . . . . . . . . . 239
xx List of Figures
10.7 EM-simulation-based comparison of DTL-CSRR and LC-tank
resonator for CMOS 96 GHz SRX design. . . . . . . . . . . 240
10.8 Schematic of CMOS 96 GHz SRX with DTL-CSRR. . . . . 241
10.9 Layout for CMOS on-chip implementation of DTL-SRR for
135 GHz SRX. . . . . . . . . . . . . . . . . . . . . . . . . . . 242
10.10 EM-simulation-based comparison of DTL-SRR and LC-tank
resonator for CMOS 135 GHz SRX design. . . . . . . . . . . 242
10.11 Impedance diagram of DTL-SRR and LC-tank in Global
Foundries 65-nm CMOS process. . . . . . . . . . . . . . . . 243
10.12 Schematic of CMOS 135 GHz SRX with DTL-SRR. . . . . . 244
10.13 Die micrographs: (a) CMOS 96 GHz SRX with DTL-CSRR,
and (b) CMO S 135 GHz SRX with DTL-SRR. . . . . . . . . 245
10.14 Measurement and simulation results of CMOS 96 GHz SRX. 246
10.15 Measurement setup of CMOS 135 GHz SRX with DTL-SRR. 247
10.16 Measurement and simulation results of CMOS 13 5 GHz SRX. 248
11.1 (a) Proposed SRX struc ture, in-phase output (E,F), and sin-
wave quench signal; (b) envelope shape response (V
P
) of oscil-
lator under different input power, and envelope detector out-
put (V
d
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
11.2 Traditional SRX circuit model and its feedback model; (b)
proposed SRX circuit model and its feedback model. . . . . 253
11.3 Circuit diagram of proposed SRX with ZPS-coupled oscilla-
tors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 55
11.4 Layout of ZPS and simulation results of inductor and Z PS. . 25 6
11.5 (a) Chip photo of 131.5 GHz SRX in 65 nm CMOS; (b)
measured self-oscillation frequency of 131.74 GHz and output
power of −23.10 dBm. . . . . . . . . . . . . . . . . . . . . . 257
11.6 Measurement results: i) the max imum gain of 41 mB; and ii)
input S
11
parameter. . . . . . . . . . . . . . . . . . . . . . . 257
11.7 Measured sensitivity of −84 dBm and the ma ximum output
voltage of 138 mV. . . . . . . . . . . . . . . . . . . . . . . . 258
12.1 Metamaterial-based THz imaging system. . . . . . . . . . . 262
12.2 THz image system with heterodyne receiver fo r high spectrum
resolution detection and circular-polarized antenna for the tol-
erance of depolarization effect. . . . . . . . . . . . . . . . . . 262
12.3 (a) PCB integration of CMOS 135-GHz SRX with antenna;
(b) THz imag ing measurement setup with the proposed re-
ceiver chip integrated on PCB and object under test fixed on
an X-Y moving stage. . . . . . . . . . . . . . . . . . . . . . . 264
12.4 Images captured by imaging system with the proposed 135 -
GHz SRX receiver: knife, perfume, and coin in handbag. . . 265
12.5 Images captured by imaging system with the proposed 135 -
GHz SRX receiver: moisturized and normal Panadol pills. . 266
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