Chapter 6
Phase-Locked Loop
6.1 Introduction
Recently, with the increasing demand for high-da ta-rate communication sys-
tem s uch as 60GHz band applications, the requirements for integrating PLLs
with an on-chip transceiver becomes more challenging. The conventional
metho dology to achieve fully coverage of the IEEE 802.15.3 c 60GHz band
(58.3–64.8GHz) by using multiple capacitor bands seems to be a good can-
didate. However, the quality factor of the tuning capacitor implemented by
MOSFET varactors is low at such high frequency, leading to lower drivability
of the VCO which in turn may make the VCO fail to lock the prescaler. In-
stead of using capacitive tuning in the VCO, in this chapter, a novel 60GHz
VCO using inductive tuning by switching return path is employed to cover
the whole band with high o utput power almost unaffected. The PLL provides
the four source frequencies defined by the IEEE 802.15.3c 60GHz communi-
cation standard with the attained phase noise suitable for various short-range
applications.
Figure 6.1 shows the schematic of the designed 60-GHz PLL. It mainly
consists of a 60-GHz VCO, a divider chain, a phase frequenc y detector (PFD),
a charge pump, a law pass filter (LPF) and a r eference clock. The 60-GHz
VCO adopts the propose d symmetric inductive tuning method in Chapter
4 to achieve a wide FTR. The divider chain includes a 60-GHz divide-by-2
divider, a 30-GHz divide-by-2 divider, a dynamic current-mode logic (DCML)
divide-by-4 divider, and a programmable divider. The LPF is realized off-chip,
and the refere nc e clock is generated through a 54-MHz crystal oscillator.
Figure 6.2 shows the implemented layout of the 60- GHz PLL in GF CMOS
65-nm technology, with an active are a of 0.68 × 0.64 mm
2
excluding pads.
135
136 Design of CMOS Millimeter-Wave and Terahertz Integrated Circuits
Figure 6 .1: Schematic of designed CMOS 60-GHz PLL.
Figure 6 .2: Layout of designed CMOS 60-GHz PLL.
One testing point is inserted after the DCML divider for tuning of bias and
debugging.
Voltage-controlled oscillator (VCO) and high-freque nc y dividers are two
majo r designing blocks in PLL at 60 GHz. Considering the required wide-
band at 60 GHz and process variation in nano-scale CMOS, a wide frequency
locking range is typically required for 60-GHz PLL de sign, which demands
the wide frequency-tuning-range (FTR) of VCO and wide locking range of a
divider. In the following sub-sections , the design details for the VCO and a
high-frequency portion of divider chain are provided.
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